Ecc Control Register (Fecc_Ctrl); Test Data Out High Register (Fecc_Fouth_Test); Test Data Out Low Register (Fecc_Foutl_Test); Ecc Test Register (Fecc_Test) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Flash Registers
Bit Field
31-8 Reserved
7-0 ECC

5.4.4.15 ECC Control Register (FECC_CTRL)

31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-144. ECC Control Register (FECC_CTRL) Field Descriptions
Bit Field
31-2 Reserved
1 ECC_SELECT
0 ECC_TEST_EN

5.4.4.16 Test Data Out High Register (FECC_FOUTH_TEST)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-145. Test Data Out High Register (FECC_FOUTH_TEST) Field Descriptions
Bit Field
31-0 DATAOUTH

5.4.4.17 Test Data Out Low Register (FECC_FOUTL_TEST)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
576
Internal Memory
Table 5-143. ECC Test Register (FECC_TEST) Field Descriptions
Value Description
0 Reserved
8-bit ECC for selected 64-bit data. User-configurable ECC bits of the selected 64-bit
data block in ECC test mode.
Figure 5-136. ECC Control Register (FECC_CTRL)
Reserved
R-0
Value Description
0 Reserved
ECC block select.
0 Selects the ECC block on bits [63:0] of bank data.
1 Selects the ECC block on bits [127:64] of bank data.
ECC test mode enable.
0 ECC test mode disabled
1 ECC test mode enabled
Figure 5-137. Test Data Out High Register (FECC_FOUTH_TEST)
Value Description
High double word test data out. Holds bits 63:32 of the data out of the selected ECC block.
Figure 5-138. Test Data Out Low Register (FECC_FOUTL_TEST)
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
DATAOUTH
R-0
DATAOUTL
R-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
2 1 0
ECC_SELECT ECC_TEST_E
N
R/W-0 R/W-0
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