Spi Fifo Control (Spiffct) Register − Address 704Ch; Spi Fifo Receive (Spiffrx) Register Field Descriptions; Spi Fifo Control (Spiffct) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

SPI Registers and Waveforms
Table 12-18. SPI FIFO Receive (SPIFFRX) Register Field Descriptions
Bit Field
15 RXFFOVF
14 RXFFOVF CLR
13 RXFIFO Reset
12-8 RXFFST4−0
7 RXFFINT
6 RXFFINT CLR
5 RXFFIENA
4-0 RXFFIL4−0
Figure 12-23. SPI FIFO Control (SPIFFCT) Register − Address 704Ch
15
7 6
FFTXDLY7 FFTXDLY6
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-19. SPI FIFO Control (SPIFFCT) Register Field Descriptions
Bit Field
15-8 Reserved
7-0 FFTXDLY7−0
1008
C28 Serial Peripheral Interface (SPI)
Value Description
Receive FIFO overflow flag
0 Receive FIFO has not overflowed. This is a read-only bit.
1 Receive FIFO has overflowed, read-only bit. More than 4 words have been received in to the FIFO,
and the first received word is lost.
Receive FIFO overflow clear
0 Write 0 does not affect RXFFOVF flag bit, Bit reads back a zero
1 Write 1 to clear RXFFOVF flag in bit 15
Receive FIFO reset
0 Write 0 to reset the FIFO pointer to zero, and hold in reset.
1 Re-enable receive FIFO operation
Receive FIFO Status
00000 Receive FIFO is empty.
00001 Receive FIFO has 1 word.
00010 Receive FIFO has 2 words.
00011 Receive FIFO has 3 words.
00100 Receive FIFO has 4 words, the maximum.
Receive FIFO interrupt
0 RXFIFO interrupt has not occurred. This is a read-only bit.
1 RXFIFO interrupt has occurred. This is a read-only bit.
Receive FIFO interrupt clear
0 Write 0 has no effect on RXFFINT flag bit, Bit reads back a zero.
1 Write 1 to clear RXFFINT flag in bit 7.
RX FIFO interrupt enable
0 RX FIFO interrupt based on RXFFIL match (greater than or equal to) will be disabled.
1 RX FIFO interrupt based on RXFFIL match (greater than or equal to) will be enabled.
Receive FIFO interrupt level bits
11111 Receive FIFO generates an interrupt when the FIFO status bits (RXFFST4–0) are greater than or
equal to the FIFO level bits (RXFFIL4–0). The default value of these bits after reset is 11111. This
avoids frequent interrupts after reset, as the receive FIFO will be empty most of the time.
5 4
FFTXDLY5 FFTXDLY4
R/W-0 R/W-0
Value Description
Reads return zero; writes have no effect.
FIFO transmit delay bits
0 These bits define the delay between every transfer from FIFO transmit buffer to transmit shift
register. The delay is defined in number SPI serial clock cycles. The 8-bit register could define a
minimum delay of 0 serial clock cycles and a maximum of 255 serial clock cycles.
1 In FIFO mode, the buffer (TXBUF) between the shift register and the FIFO should be filled only
after the shift register has completed shifting of the last bit. This is required to pass on the delay
between transfers to the data stream. In the FIFO mode TXBUF should not be treated as one
additional level of buffer.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3 2
FFTXDLY3 FFTXDLY2
R/W-0 R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
8
1 0
FFTXDLY1 FFTXDLY0
R/W-0 R/W-0
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