Sci Receiver Status Register (Scirxst) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 13-13. SCI Receiver Status Register (SCIRXST) Field Descriptions
Bit Field
7 RX ERROR
6 RXRDY
5 BRKDT
4 FE
3 OE
2 PE
1 RXWAKE
0 Reserved
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
SCI receiver error flag. The RX ERROR flag indicates that one of the error flags in the receiver
status register is set. RX ERROR is a logical OR of the break detect, framing error, overrun, and
parity error enable flags (bits 5−2: BRKDT, FE, OE, and PE).
A 1 on this bit will cause an interrupt if the RX ERR INT ENA bit (SCICTL1.6) is set. This bit can be
used for fast error-condition checking during the interrupt service routine. This error flag cannot be
cleared directly; it is cleared by an active SW RESET or by a system reset.
0 No error flags set
1 Error flag(s) set
SCI receiver-ready flag. When a new character is ready to be read from the SCIRXBUF register,
the receiver sets this bit, and a receiver interrupt is generated if the RX/BK INT ENA bit
(SCICTL2.1) is a 1. RXRDY is cleared by a reading of the SCIRXBUF register, by an active SW
RESET, or by a system reset.
0 No new character in SCIRXBUF
1 Character ready to be read from SCIRXBUF
SCI break-detect flag. The SCI sets this bit when a break condition occurs. A break condition
occurs when the SCI receiver data line (SCIRXD) remains continuously low for at least ten bits,
beginning after a missing first stop bit. The occurrence of a break causes a receiver interrupt to be
generated if the RX/BK INT ENA bit is a 1, but it does not cause the receiver buffer to be loaded. A
BRKDT interrupt can occur even if the receiver SLEEP bit is set to 1. BRKDT is cleared by an
active SW RESET or by a system reset. It is not cleared by receipt of a character after the break is
detected. In order to receive more characters, the SCI must be reset by toggling the SW RESET bit
or by a system reset.
0 No break condition
1 Break condition occurred
SCI framing-error flag. The SCI sets this bit when an expected stop bit is not found. Only the first
stop bit is checked. The missing stop bit indicates that synchronization with the start bit has been
lost and that the character is incorrectly framed. The FE bit is reset by a clearing of the SW RESET
bit or by a system reset.
0 No framing error detected
1 Framing error detected
SCI overrun-error flag. The SCI sets this bit when a character is transferred into registers
SCIRXEMU and SCIRXBUF before the previous character is fully read by the CPU or DMAC. The
previous character is overwritten and lost. The OE flag bit is reset by an active SW RESET or by a
system reset.
0 No overrun error detected
1 Overrun error detected
SCI parity-error flag. This flag bit is set when a character is received with a mismatch between the
number of 1s and its parity bit. The address bit is included in the calculation. If parity generation
and detection is not enabled, the PE flag is disabled and read as 0. The PE bit is reset by an active
SW RESET or a system reset.!
0 No parity error or parity is disabled
1 Parity error is detected
Receiver wake-up-detect flag
0 No detection of a receiver wake-up condition
1 A value of 1 in this bit indicates detection of a receiver wake-up condition. In the address-bit
multiprocessor mode (SCICCR.3 = 1), RXWAKE reflects the value of the address bit for the
character contained in SCIRXBUF. In the idle-line multiprocessor mode, RXWAKE is set if the
SCIRXD data line is detected as idle. RXWAKE is a read-only flag, cleared by one of the following:
• The transfer of the first byte after the address byte to SCIRXBUF (only in non-FIFO mode)
• The reading of SCIRXBUF
• An active SW RESET
• A system reset
Reads return zero; writes have no effect.
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C28 Serial Communications Interface (SCI)
SCI Registers
1037