Dead-Band Generator Control Register (Dbctl); Dead-Band Generator Control Register (Dbctl) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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7.4.4 Dead-Band Submodule Registers
Figure 7-104 through
15 14
HALFCYCLE DEDB_MODE
R/W-0
7 6
LOADREDMODE
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-54. Dead-Band Generator Control Register (DBCTL) Field Descriptions
Bit Field
15 HALFCYCLE
14 DEDB_MODE
13-12 OUTSWAP
11 SHDWDBFEDMODE
10 SHDWDBREDMODE
SPRUHE8E – October 2012 – Revised November 2019
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Figure 7-106 and Table 7-54
Figure 7-104. Dead-Band Generator Control Register (DBCTL)
13 12
OUTSWAP
5 4
IN_MODE
R/W-0
Value Description
Half Cycle Clocking Enable Bit
0 Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate.
1 Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2.
Dead Band Dual-Edge B Mode Control (S8 switch)
0 Rising edge delay applied to InA/InB as selected by S4 switch (IN-MODE bits) on A
signal path only. Falling edge delay applied to InA/InB as selected by S5 switch (IN-
MODE bits) on B signal path only.
1 Rising edge delay and falling edge delay applied to source selected by S4 switch (IN-
MODE bits) and output to B signal path only. Note: When this bit is set to 1, user should
always either set OUT_MODE bits such that Apath = InA OR OUTSWAP bits such that
OutA=Bpath; otherwise, OutA will be invalid.
Dead Band Output Swap Control
Bit 13 controls the S7 switch and bit 12 controls the S6 switch shown in
00 OutA and OutB signals are as defined by OUT-MODE bits.
01 OutA = A-path as defined by OUT-MODE bits.
OutB = A-path as defined by OUT-MODE bits (rising edge delay or delay-bypassed A-
signal path).
10 OutA = B-path as defined by OUT-MODE bits (falling edge delay or delay-bypassed B-
signal path).
OutB = B-path as defined by OUT-MODE bits.
11 OutA = B-path as defined by OUT-MODE bits (falling edge delay or delay-bypassed B-
signal path).
OutB = A-path as defined by OUT-MODE bits (rising edge delay or delay-bypassed A-
signal path).
FED Dead-Band Load Mode
0 Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU
directly access the active register for immediate "FED dead-band action."
1 Shadow mode. Operates as a double buffer. All writes via the CPU access Shadow
register. Default at Reset is Immediate mode (for compatibility with legacy).
RED Dead Band Load mode
0 Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU
directly access the active register for immediate "RED dead-band action."
1 Shadow mode. Operates as a double buffer. All writes via the CPU access the Shadow
register. Default at Reset is Immediate mode (for compatibility with legacy).
Copyright © 2012–2019, Texas Instruments Incorporated
through Table 7-56 provide the register definitions.
11 10
SHDWDBFED SHDWDBRED
MODE MODE
3 2
POLSEL
R/W-0
C28 Enhanced Pulse Width Modulator (ePWM) Module
Registers
9 8
LOADFEDMODE
1 0
OUT_MODE
R/W-0
Figure 7-31.
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