M3 Ram Error Registers; Mtoc_Msg_Ram Initdone Register (Mtocrinitdone); M3 Cpu Uncorrectable Write Error Address Register (Mcuncweaddr); M3 Μdma Uncorrectable Write Error Address Register (Mduncweaddr) - Texas Instruments Concerto F28M36 Series Technical Reference Manual

RAM Control Module Registers

5.2.1.15 MTOC_MSG_RAM INITDONE Register (MTOCRINITDONE)

Figure 5-18. MTOC_MSG_RAM INITDONE Register (MTOCRINITDONE)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-27. MTOC_MSG_RAM INITDONE Register (MTOCRINITDONE) Field Descriptions
Bit Field
31-1 Reserved
0 RAMINITDONE
MTOCMSGRAM

5.2.2 M3 RAM Error Registers

5.2.2.1

M3 CPU Uncorrectable Write Error Address Register (MCUNCWEADDR)

Figure 5-19. M3 CPU Uncorrectable Write Error Address Register (MCUNCWEADDR)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-28. M3 CPU Uncorrectable Write Error Address Register (MCUNCWEADDR) Field
Bit Field
31-0 MCUNCWEADD
R
5.2.2.2 M3 µDMA Uncorrectable Write Error Address Register (MDUNCWEADDR)
Figure 5-20. M3 µDMA Uncorrectable Write Error Address Register (MDUNCWEADDR)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-29. M3 µDMA Uncorrectable Write Error Address Register (MDUNCWEADDR) Field
Bit Field
31-0 MDUNCWEADD
R
494
Internal Memory
Reserved
R-0
Value Description
Reserved
RAM Initialization Status when RAMINIT is Set for MTOC_MSG_RAM Block
0 RAM initialization is not finished for MTOC_MSG_RAM block.
1 RAM initialization is done for MTOC_MSG_RAM block. MTOC_MSG_RAM can be accessed by M3
CPU/µDMA.
This status bit gets cleared when the RAMINIT bit is set for CMTOC_MSG_RAM block.
MCUNCWEADDR
Value Description
This register contains the address where uncorrectable error occurs during M3 CPU byte writes.
Only the address coresponding to the last error is stored.
MDUNCWEADDR
Value Description
This register contains the address where uncorrectable error occurs during M3 µDMA byte writes.
Only the address coresponding to the last error is stored.
Copyright © 2012–2019, Texas Instruments Incorporated
R-0
Descriptions
R-0
Descriptions
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
1 0
RAMINITDONE
MTOCMSGRAM
R-0
0
0
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