Table of Contents
Advertisement
Enhanced SPI Module Overview
Data written to SPIDAT or SPITXBUF is transmitted to the network when appropriate edges of the
SPICLK signal are received from the network master. Data written to the SPITXBUF register will be
transferred to the SPIDAT register when all bits of the character to be transmitted have been shifted out of
SPIDAT. If no character is currently being transmitted when SPITXBUF is written to, the data will be
transferred immediately to SPIDAT. To receive data, the SPI waits for the network master to send the
SPICLK signal and then shifts the data on the SPISIMO pin into SPIDAT. If data is to be transmitted by
the slave simultaneously, and SPITXBUF has not been previously loaded, the data must be written to
SPITXBUF or SPIDAT before the beginning of the SPICLK signal.
When the TALK bit (SPICTL.1) is cleared, data transmission is disabled, and the output line (SPISOMI) is
put into the high-impedance state. If this occurs while a transmission is active, the current character is
completely transmitted even though SPISOMI is forced into the high-impedance state. This ensures that
the SPI is still able to receive incoming data correctly. This TALK bit allows many slave devices to be tied
together on the network, but only one slave at a time is allowed to drive the SPISOMI line.
The SPISTE pin operates as the slave-select pin. An active-low signal on the SPISTE pin allows the slave
SPI to transfer data to the serial data line; an inactive- high signal causes the slave SPI serial shift register
to stop and its serial output pin to be put into the high-impedance state. This allows many slave devices to
be tied together on the network, although only one slave device is selected at a time.
12.1.5 SPI Interrupts
This section includes information on the control bits that initialize interrupts, data format, clocking,
initialization, and data transfer.
12.1.5.1 SPI Interrupt Control Bits
Five control bits are used to initialize the SPI interrupts:
•
SPI INT ENA bit (SPICTL.0)
•
SPI INT FLAG bit (SPISTS.6)
•
OVERRUN INT ENA bit (SPICTL.4)
•
RECEIVER OVERRUN FLAG bit (SPISTS.7)
12.1.5.1.1 SPI INT ENA Bit (SPICTL.0)
When the SPI interrupt-enable bit is set and an interrupt condition occurs, the corresponding interrupt is
asserted.
0
Disable SPI interrupts
1
Enable SPI interrupts
12.1.5.1.2 SPI INT FLAG Bit (SPISTS.6)
This status flag indicates that a character has been placed in the SPI receiver buffer and is ready to be
read.
When a complete character has been shifted into or out of SPIDAT, the SPI INT FLAG bit (SPISTS.6) is
set, and an interrupt is generated if enabled by the SPI INT ENA bit (SPICTL.0). The interrupt flag remains
set until it is cleared by one of the following events:
•
The interrupt is acknowledged.
•
The CPU reads the SPIRXBUF (reading the SPIRXEMU does not clear the SPI INT FLAG bit).
•
The device enters IDLE2 or HALT mode with an IDLE instruction.
•
Software clears the SPI SW RESET bit (SPICCR.7).
•
A system reset occurs.
When the SPI INT FLAG bit is set, a character has been placed into the SPIRXBUF and is ready to be
read. If the CPU does not read the character by the time the next complete character has been received,
the new character is written into SPIRXBUF, and the RECEIVER OVERRUN Flag bit (SPISTS.7) is set.
988
C28 Serial Peripheral Interface (SPI)
Copyright © 2012–2019, Texas Instruments Incorporated
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
www.ti.com
Advertisement
Chapters
Table of Contents
