Sci Fifo Receive (Sciffrx) Register - Address 705Bh; Sci Fifo Receive (Sciffrx) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

SCI Registers
Table 13-15. SCI FIFO Transmit (SCIFFTX) Register Field Descriptions (continued)
Bit Field
13 TXFIFO Reset
12-8 TXFFST4-0
7 TXFFINT Flag
6 TXFFINT CLR
5 TXFFIENA
4-0 TXFFIL4-0
Figure 13-23. SCI FIFO Receive (SCIFFRX) Register — Address 705Bh
15 14
RXFFOVF RXFFOVR CLR
R-0 W−0
7 6
RXFFINT Flag RXFFINT CLR
R-0 W−0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-16. SCI FIFO Receive (SCIFFRX) Register Field Descriptions
Bit Field
15 RXFFOVF
14 RXFFOVR CLR
13 RXFIFO Reset
1040
C28 Serial Communications Interface (SCI)
Value Description
Transmit FIFO reset
0 Reset the FIFO pointer to zero and hold in reset
1 Re-enable transmit FIFO operation
00000 Transmit FIFO is empty.
00001 Transmit FIFO has 1 words
00010 Transmit FIFO has 2 words
00011 Transmit FIFO has 3 words
0xxxx Transmit FIFO has x words
10000 Transmit FIFO has 16 words
Transmit FIFO interrupt
0 TXFIFO interrupt has not occurred, read-only bit
1 TXFIFO interrupt has occurred, read-only bit
Transmit FIFO clear
0 Write 0 has no effect on TXFIFINT flag bit, Bit reads back a zero
1 Write 1 to clear TXFFINT flag in bit 7
Transmit FIFO interrupt enable
0 TX FIFO interrupt based on TXFFIL match (less than or equal to) is disabled
1 TX FIFO interrupt based on TXFFIL match (less than or equal to) is enabled.
TXFFIL4−0 Transmit FIFO interrupt level bits.
The transmit FIFO generates an interrupt whenever the FIFO status bits (TXFFST4-0) are less than
or equal to the FIFO level bits (TXFFIL4-0). The maximum value that can be assigned to these bits
to generate an interrupt cannot be more than the depth of the TX FIFO. The default value of these
bits after reset is 00000b. Users should set TXFFIL to best fit their application needs by weighing
between the CPU overhead to service the ISR and the best possible usage of SCI bus bandwidth.
13 12
RXFIFO Reset RXFIFST4
R/W−1 R-0
5 4
RXFFIENA RXFFIL4
R/W−0 R/W−1
Value Description
Receive FIFO overflow. This will function as flag, but cannot generate interrupt by itself. This
condition will occur while receive interrupt is active. Receive interrupts should service this flag
condition.
0 Receive FIFO has not overflowed, read-only bit
1 Receive FIFO has overflowed, read-only bit. More than 16 words have been received in to the
FIFO, and the first received word is lost
RXFFOVF clear
0 Write 0 has no effect on RXFFOVF flag bit. Bit reads back a zero
1 Write 1 to clear RXFFOVF flag in bit 15
Receive FIFO reset
0 Write 0 to reset the FIFO pointer to zero, and hold in reset.
1 Re-enable receive FIFO operation
Copyright © 2012–2019, Texas Instruments Incorporated
11 10
RXFFST3 RXFFST2
R-0 R-0
3 2
RXFFIL3 RXFFIL2
R/W−1 R/W−1
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
9 8
RXFFST1 RXFFST0
R-0 R-0
1 0
RXFFIL1 RXFFIL0
R/W−1 R/W−1
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