Non-Blocking Reads - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Functional Description
Main read and write operations can be performed in subsets of the range 0x6000.0000 to 0xDFFF.FFFF.
A read from an address mapped location uses the offset and size to control the address and size of the
external operation. When performing a multi-value load, the read is done as a burst (when available)to
maximize performance. A write to an address mapped location uses the offset and size to control the
address and size of the external operation. When performing a multi-value store, the write is done as a
burst (when available) to maximize performance.
NAND Flash memory (x8) can be read natively. Automatic programming support is not provided;
programming must be done by the user following the manufacturer's protocol. Automatic page ECC is also
not supported, but can be performed in software.

17.3.1 Non-Blocking Reads

The EPI Controller supports a special kind of read called a non-blocking read, also referred to as a posted
read. Where a normal read stalls the processor or µDMA until the data is returned, a non-blocking read is
performed in the background.
A non-blocking read is configured by writing the start address into a EPIRADDRn register, the size per
transaction into a EPIRSIZEn register, and then the count of operations into a EPIRPSTDn register. After
each read is completed, the result is written into the NBRFIFO and the EPIRADDRn register is
incremented by the size (1, 2, or 4). The three most significant bits of EPIRADDRn register are only
relevant in the Host Bus multi-chip select mode when they are used to enable the different chip selects.
If the NBRFIFO is filled, then the reads pause until space is made available. The NBRFIFO can be
configured to interrupt the processor or trigger the µDMA based on fullness using the EPIFIFOLVL
register. By using the trigger/interrupt method, the µDMA (or processor)can keep space available in the
NBRFIFO and allow the reads to continue unimpeded.
When performing non-blocking reads, the SDRAM controller issues two additional read transactions after
the burst request is terminated. The data for these additional transfers is discarded. This situation is
transparent to the user other than the additional EPI bus activity and can safely be ignored.
Two non-blocking read register sets are available to allow sequencing and ping-pong use. When one
completes, the other then activates. So, for example, if 20 words are to be read from 0x100 and 10 words
from 0x200, the EPIRPSTD0 register can be set up with the read from 0x100 (with a count of 20), and the
EPIRPSTD1 register can be set up with the read from 0x200 (with a count of 10). When EPIRPSTD0
finishes (count goes to 0), the EPIRPSTD1 register then starts its operation. The NBRFIFO has then
passed 30 values. When used with the µDMA, it may transfer 30 values (simple sequence), or the
primary/alternate model may be used to handle the first 20 in one way and the second 10 in another. It is
also possible to reload the EPIRPSTD0 register when it is finished (and the EPIRPSTD1 register is
active); thereby, keeping the interface constantly busy.
To cancel a non-blocking read, the EPIRPSTDn register is cleared. Care must be taken, however, if the
register set was active to drain away any values read into the NBRFIFO and ensure that any read in
progress is allowed to complete.
To ensure that the cancel is complete, the following algorithm is used (using the EPIRPSTD0 register for
example):
EPIRPSTD0 = 0;
while ((EPISTAT & 0x11) == 0x10)
; // we are active and busy
// if here, then other one is active or interface no longer busy
cnt = (EPIRADDR0 - original_address)/ EPIRSIZE0; // count of values read
cnt -= values_read_so_far;
// cnt is now number left in FIFO
while (cnt--)
value = EPIREADFIFO; // drain
1230
External Peripheral Interface (EPI)
Copyright © 2012–2019, Texas Instruments Incorporated
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
www.ti.com