By Half Clock Cycle. Inactive Level Is Low.) - Texas Instruments Concerto F28M36 Series Technical Reference Manual

www.ti.com
Figure 12-26. CLOCK POLARITY = 0, CLOCK PHASE = 1 (All data transitions are during the rising edge,
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
but delayed by half clock cycle. Inactive level is low.)
Copyright © 2012–2019, Texas Instruments Incorporated
SPI Registers and Waveforms
Ch1 Period
200 ns
SPICLK
SPISIMO
C28 Serial Peripheral Interface (SPI)
1011