Uart Interrupt Fifo Level Select (Uartifls) Register; Uart Interrupt Fifo Level Select (Uartifls) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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21.7.9 UART Interrupt FIFO Level Select (UARTIFLS) Register, offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the
FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the level.
That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if
the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the
9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the
half-way mark.
Figure 21-16. UART Interrupt FIFO Level Select (UARTIFLS) Register
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21-11. UART Interrupt FIFO Level Select (UARTIFLS) Register Field Descriptions
Bit Field
31-6 Reserved
5-3 RXIFLSEL
2-0 TXIFLSEL
SPRUHE8E – October 2012 – Revised November 2019
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Reserved
R-0
Value Description
Reserved
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
0x0 RX FIFO ≥ 1/8 full
0x1 RX FIFO ≥ 1/4 full
0x2 RX FIFO ≥ 1/2 full (default)
0x3 RX FIFO ≥ 3/4 full
0x4 RX FIFO ≥ 7/8 full
0x5–0x Reserved
7
UART Transmit Interrupt FIFO Level Select
Note: If the EOT bit in UARTCTL is set, the transmit interrupt is generated once the FIFO is
completely empty and all data including stop bits have left the transmit serializer. In this case, the
setting of TXIFLSEL is ignored.
The trigger points for the transmit interrupt are as follows:
TX FIFO ≤ 1/8 full
0x0
0x1 TX FIFO ≤ 1/4 full
0x2 TX FIFO ≤ 1/2 full (default)
0x3 TX FIFO ≤ 3/4 full
0x4 TX FIFO ≤ 7/8 full
0x5–0x Reserved
7
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Reserved
R-0
6 5
RXIFLSEL
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Register Descriptions
3 2
TXIFLSEL
R/W-2 R/W-2
16
0
1507