Interrupt 96-127 Set Enable 3 (En3) Register; Interrupt 128-133 Set Enable 4 (En4) Register; Interrupt 96-127 Set Enable 3 (En3) Register Field Descriptions; Interrupt 128-133 Set Enable 4 (En4) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

NVIC Register Descriptions
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not
enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates
the interrupt, regardless of its priority.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-14. Interrupt 96-127 Set Enable 3 (EN3) Register Field Descriptions
Bit Field
31-0 INT
25.5.5 Interrupt 128-133 Set Enable 4 (EN4), offset 0x110
The Interrupt 128-133 Set Enable (EN4) register enables interrupts and shows which interrupts are
enabled. Bit 0 corresponds to Interrupt 128; bit 5 corresponds to Interrupt 133. See the Cortex-M3
Processor chapter for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not
enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates
the interrupt, regardless of its priority.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-15. Interrupt 128-133 Set Enable 4 (EN4) Register Field Descriptions
Bit Field
31-6 Reserved
5-0 INT
1650
Cortex-M3 Peripherals
Figure 25-8. Interrupt 96-127 Set Enable 3 (EN3) Register
Value Description
Interrupt Enable
0 On a read, indicates the interrupt is disabled. On a write, no effect.
1 On a read, indicates the interrupt is enabled. On a write, enables the interrupt.
A bit can only be cleared by setting the corresponding INT[n] bit in the DIS3 register.
Figure 25-9. Interrupt 128-133 Set Enable 4 (EN4) Register
Reserved
R-0
Value Description
Reserved
Interrupt Enable
0 On a read, indicates the interrupt is disabled. On a write, no effect.
1 On a read, indicates the interrupt is enabled. On a write, enables the interrupt.
A bit can only be cleared by setting the corresponding INT[n] bit in the DIS3 register.
Copyright © 2012–2019, Texas Instruments Incorporated
INT
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
0
6 5 0
INT
R/W-0
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