Vector Table Offset (Vtable) Register; Vector Table Offset (Vtable) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

System Control Block (SCB) Register Descriptions
25.6.4 Vector Table Offset (VTABLE) Register, offset 0xD08
The Vector Table Offset (VTABLE) register indicates the offset of the vector table base address from
memory address 0x0000.0000.
Note: This register can only be accessed from privileged mode.
31 30 29
Reserved BASE
R-0
15
OFFSET
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-30 Reserved
29 BASE
28-9 OFFSET
8-0 Reserved
1670
Cortex-M3 Peripherals
Figure 25-35. Vector Table Offset (VTABLE) Register
28
9
Table 25-41. Vector Table Offset (VTABLE) Field Descriptions
Value Description
Reserved
Vector Table Base
0 The vector table is in the code memory region
1 The vector table is in the SRAM memory region
Vector Table Offset
00h When configuring the OFFSET field, the offset must be aligned to the number of exception entries
in the vector table. Because there are 91 interrupts, the minimum alignment is 128 words.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
OFFSET
R/W-0
8
SPRUHE8E – October 2012 – Revised November 2019
Reserved
R-0
Submit Documentation Feedback
www.ti.com
16
0