Enabling Interrupt; Interrupt Vector Table Mapping - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Interrupt Handling Process
Standard
DSP in real-time mode and halted
The CPU then prepares to service the interrupt. This preparation process is described in detail in
TMS320x28x DSP CPU and Instruction Set Reference Guide (literature number SPRU430). In
preparation, the corresponding CPU IFR and IER bits are cleared, EALLOW and LOOP are cleared, INTM
and DBGM are set, the pipeline is flushed and the return address is stored, and the automatic context
save is performed. The vector of the ISR is then fetched from the PIE module. If the interrupt request
comes from a multiplexed interrupt, the PIE module uses the PIEIERx and PIEIFRx registers to decode
which interrupt needs to be serviced.
The address for the interrupt service routine that is executed is fetched directly from the PIE interrupt
vector table. There is one 32-bit vector for each of the possible 96 interrupts within the PIE. Interrupt flags
within the PIE module (PIEIFRx.y) are automatically cleared when the interrupt vector is fetched. The PIE
acknowledge bit for a given interrupt group, however, must be cleared manually when ready to receive
more interrupts from the PIE group.
1.5.4.2 Vector Table Mapping
On the control subsystem, the interrupt vector table can be mapped to four distinct locations in memory. In
practice only the PIE vector table mapping is used.
This vector mapping is controlled by the following mode bits/signals:
VMAP
M0M1MAP
ENPIE
Using these bits and signals the possible vector table mappings are shown in
Vector MAPS
(1)
M1 Vector
(1)
M0 Vector
BROM Vector
PIE Vector
(1)
Vector map M0 and M1 Vector is a reserved mode only. On the 28x devices these are used as SARAM.
The M1 and M0 vector table mapping are reserved for TI testing only. When using other vector mappings,
the M0 and M1 memory blocks are treated as SARAM blocks and can be used freely without any
restrictions.
After a device reset operation, the vector table is mapped as shown in
SPRUHE8E – October 2012 – Revised November 2019
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Table 1-9. Enabling Interrupt
VMAP is found in Status Register 1 ST1 (bit 3). A device reset sets this bit to 1. The
state of this bit can be modified by writing to ST1 or by SETC/CLRC VMAP
instructions. For normal operation leave this bit set.
M0M1MAP is found in Status Register 1 ST1 (bit 11). A device reset sets this bit to 1.
The state of this bit can be modified by writing to ST1 or by SETC/CLRC M0M1MAP
instructions. For normal device operation, this bit should remain set. M0M1MAP = 0 is
reserved for TI testing only.
ENPIE is found in PIECTRL Register (bit 0). The default value of this bit, on reset, is
set to 0 (PIE disabled). The state of this bit can be modified after reset by writing to the
PIECTRL register (address 0x0000 0CE0).
Table 1-10. Interrupt Vector Table Mapping
Vectors Fetched From
M1 SARAM Block 0x000000 - 0x00003F
M0 SARAM Block 0x000000 - 0x00003F
Boot ROM Block 0x3FFFC0 - 0x3FFFFF
PIE Block 0x000D00 - 0x000DFF
Copyright © 2012–2019, Texas Instruments Incorporated
Interrupt Enabled If"¦
INTM = 0 and bit in IER is 1
Bit in IER is 1 and DBGIER is 1
Address Range VMAP
0
0
1
1
Exceptions and Interrupts Control
Table 1-10.
M0M1MAP
0
1
X
X
Table 1-11.
System Control and Interrupts
ENPIE
X
X
0
1
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