Analog I/O Mux 1 (Aiomux1) Register; Analog I/O Mux 2 (Aiomux2) Register; Analog I/O Mux 1 (Aiomux1) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

C28 General-Purpose Input/Output (GPIO)
31 30 29 28
Reserved AIO14
R/W-0x2 R/W-0x2
15 14 13 12
Reserved AIO6
R/W-0x2 R/W-0x2
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-61. Analog I/O MUX 1 (AIOMUX1) Register Field Descriptions
Bit Field
31:30 Reserved
29:28 AIO14
27:26 Reserved
25:24 AIO12
23:22 Reserved
21:20 AIO10
19:14 Reserved
13:12 AIO6
11:10 Reserved
9:8 AIO4
7:6 Reserved
5:4 AIO2
3:0 Reserved

4.2.7.12 Analog I/O MUX 2 (AIOMUX2) Register

The Analog I/O MUX 2 (AIOMUX2) register is shown and described in the figure and table below.
31 30 29 28
Reserved AIO30
R/W-0x2 R/W-0x2
15 14 13 12
Reserved AIO22
R/W-0x2 R/W-0x2
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
422
General-Purpose Input/Output (GPIO)
Figure 4-52. Analog I/O MUX 1 (AIOMUX1) Register
27 26 25
Reserved AIO12
R/W-0x2 R/W-0x2
11 10 9
Reserved AIO4
R/W-0x2 R/W-0x2
Value Description
Any writes to these bit(s) must always have a value of 2.
00 or 01 AIO14 enabled
10 or 11 AIO14 disabled (default)
Any writes to these bit(s) must always have a value of 2.
00 or 01 AIO12 enabled
10 or 11 AIO12 disabled (default)
Any writes to these bit(s) must always have a value of 2.
00 or 01 AIO10 enabled
10 or 11 AIO10 disabled (default)
Any writes to these bit(s) must always have a value of 2.
00 or 01 AIO6 enabled
10 or 11 AIO6 disabled (default)
Any writes to these bit(s) must always have a value of 2.
00 or 01 AIO4 enabled
10 or 11 AIO4 disabled (default)
Any writes to these bit(s) must always have a value of 2.
00 or 01 AIO2 enabled
10 or 11 AIO2 disabled (default)
Any writes to these bit(s) must always have a value of 2.
Figure 4-53. Analog I/O MUX 2 (AIOMUX2) Register
27 26 25
Reserved AIO28
R/W-0x2 R/W-0x2
11 10 9
Reserved AIO20
R/W-0x2 R/W-0x2
Copyright © 2012–2019, Texas Instruments Incorporated
24 23 22 21
Reserved AIO10
R/W-0x2 R/W-0x2
8 7 6 5
Reserved AIO2
R/W-0x2 R/W-0x2
24 23 22 21
Reserved AIO26
R/W-0x2 R/W-0x2
8 7 6 5
Reserved AIO18
R/W-0x2 R/W-0x2
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
20 19
Reserved
R/W-0xA
4 3
Reserved
R/W-0xA
20 19
Reserved
R/W-0xA
4 3
Reserved
R/W-0xA
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