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Programming Model
L L ow registers
High registers
Stack Pointer
Link Register
Program Counter
Name
Type
R0
R/W
R1
R/W
R2
R/W
R3
R/W
R4
R/W
R5
R/W
R6
R/W
R7
R/W
R8
R/W
R9
R/W
R10
R/W
R11
R/W
R12
R/W
SP
R/W
LR
R/W
PC
R/W
PSR
R/W
PRIMASK
R/W
FAULTMASK
R/W
BASEPRI
R/W
CONTROL
R/W
1608
Cortex-M3 Processor
Figure 24-2. Cortex-M3 Register Set
R0
R1
R2
R3
R4
R5
R6
General-purpose registers
R7
R8
R9
R10
R11
R12
‡
SP (R13)
PSP
LR (R14)
PC (R15)
PSR
Program status register
PRIMASK
FAULTMASK
Exception mask registers
BASEPRI
CONTROL
CONTROL register
Table 24-2. Processor Register Map
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0xFFFF.FFFF
-
0x0100.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Copyright © 2012–2019, Texas Instruments Incorporated
‡
MSP
‡
Banked version of SP
Special registers
Description
Cortex General-Purpose Register 0
Cortex General-Purpose Register 1
Cortex General-Purpose Register 2
Cortex General-Purpose Register 3
Cortex General-Purpose Register 4
Cortex General-Purpose Register 5
Cortex General-Purpose Register 6
Cortex General-Purpose Register 7
Cortex General-Purpose Register 8
Cortex General-Purpose Register 9
Cortex General-Purpose Register 10
Cortex General-Purpose Register 11
Cortex General-Purpose Register 12
Stack Pointer
Link Register
Program Counter
Program Status Register
Priority Mask Register
Fault Mask Register
Base Priority Mask Register
Control Register
SPRUHE8E – October 2012 – Revised November 2019
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