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18.2.2.5 Babble
The USB Host controller does not start a transaction until the bus has been inactive for at least the
minimum inter-packet delay. The controller also does not start a transaction unless it can be finished
before the end of the frame. If the bus is still active at the end of a frame, then the USB Host controller
assumes that the target device to which it is connected has malfunctioned, and the USB controller
suspends all transactions and generates a babble interrupt.
18.2.2.6 Host SUSPEND
If the SUSPEND bit in the USBPOWER register is set, the USB Host controller completes the current
transaction then stops the transaction scheduler and frame counter. No further transactions are started
and no SOF packets are generated.
To exit SUSPEND mode, set the RESUME bit and clear the SUSPEND bit. While the RESUME bit is set,
the USB Host controller generates RESUME signaling on the bus. After 20 ms, the RESUME bit must be
cleared, at which point the frame counter and transaction scheduler start. The Host supports the detection
of a remote wake-up.
18.2.2.7 USB RESET
If the RESET bit in the USBPOWER register is set, the USB Host controller generates USB RESET
signaling on the bus. The RESET bit must be set for at least 20 ms to ensure correct resetting of the
target device. After the CPU has cleared the bit, the USB Host controller starts its frame counter and
transaction scheduler.
18.2.2.8 Connect/Disconnect
A session is started by setting the SESSION bit in the USB device Control (USBDEVCTL) register,
enabling the USB controller to wait for a device to be connected. When a device is detected, a connect
interrupt is generated. The speed of the device that has been connected can be determined by reading
the USBDEVCTL register where the FSDEV bit is set for a full-speed device, and the LSDEV bit is set for
a low-speed device. The USB controller must generate a RESET to the device, and then the USB Host
controller can begin device enumeration. If the device is disconnected while a session is in progress, a
disconnect interrupt is generated.
18.2.3 OTG Mode
To conserve power, the USB On-The-Go (OTG) supplement allows VBUS to only be powered up when
required and to be turned off when the bus is not in use. VBUS is always supplied by the A device on the
bus. The USB OTG controller determines whether it is the A device or the B device by sampling the ID
input from the PHY. This signal is pulled Low when an A-type plug is sensed (signifying that the USB OTG
controller should act as the A device) but taken High when a B-type plug is sensed (signifying that the
USB controller is a B device). Note that when switching between OTG A and OTG B, the USB controller
retains all register contents.
18.2.3.1 Starting a Session
When the USB OTG controller is ready to start a session, the SESSION bit must be set in the
USBDEVCTL register. The USB OTG controller then enables ID pin sensing. The ID input is either taken
Low if an A-type connection is detected or High if a B-type connection is detected. The DEV bit in the
USBDEVCTL register is also set to indicate whether the USB OTG controller has adopted the role of the A
device or the B device. The USB OTG controller also provides an interrupt to indicate that ID pin sensing
has completed and the mode value in the USBDEVCTL register is valid. This interrupt is enabled in the
USBIDVIM register, and the status is checked in the USBIDVISC register. As soon as the USB controller
has detected that it is on the A side of the cable, it must enable VBUS power within 100ms or the USB
controller reverts to Device mode.
SPRUHE8E – October 2012 – Revised November 2019
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Copyright © 2012–2019, Texas Instruments Incorporated
Functional Description
M3 Universal Serial Bus (USB) Controller
1325
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