Master Access Violation Flag Clear Register (Cmavclr); Master Access Violation Flag Clear Register (Cmavclr) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

RAM Control Module Registers

5.2.4.19 Master Access Violation Flag Clear Register (CMAVCLR)

Figure 5-74. Master Access Violation Flag Clear Register (CMAVCLR)
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-83. Master Access Violation Flag Clear Register (CMAVCLR) Field Descriptions
Bit Field
31-3 Reserved
2 CPUWRITE
1 DMAWRITE
0 CPUFETCH
532
Internal Memory
Reserved
R-0
Value Description
Reserved
Master CPU Write Access Violation Clea. Any reads to this bit will return a 0.
0 No effect.
1 Clears the corresponding master CPU write access violation flag.
Master DMA Write Access Violation Clear. Any reads to this bit will return a 0.
0 No effect.
1 Clears the corresponding master DMA write access violation flag.
Master CPU Fetch Access Violation Clear. Any reads to this bit will return a 0.
0 No effect.
1 Clears the corresponding master CPU fetch access violation flag.
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Reserved
R-0
3 2
CPUWRITE
R/W=1-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
16
1 0
DMAWRITE CPUFETCH
R/W=1-0 R/W=1-0
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