M3 Uncorrectable Error Flag Clear Register (Mueclr); M3 Corrected Error Counter Register (Mcecntr); M3 Uncorrectable Error Flag Clear Register (Mueclr) Field Descriptions; M3 Corrected Error Counter Register (Mcecntr) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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M3 Uncorrectable Error Flag Clear Register (MUECLR)

Figure 5-27. M3 Uncorrectable Error Flag Clear Register (MUECLR)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-36. M3 Uncorrectable Error Flag Clear Register (MUECLR) Field Descriptions

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-37. M3 Corrected Error Counter Register (MCECNTR) Field Descriptions

SPRUHE8E – October 2012 – Revised November 2019

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M3 µDMA Uncorrectable Read Error Clear. Any reads to this bit will return a 0.

Clears the M3 µDMA uncorrectable read error flag.

M3 CPU Uncorrectable Read Error Clear. Any reads to this bit will return a 0.

Clears the M3 CPU uncorrectable read error flag.

M3 µDMA Uncorrectable Write Error Clear. Any reads to this bit will return a 0.

Clears the M3 µDMA uncorrectable write error flag.

M3 CPU Uncorrectable Write Error Clear. Any reads to this bit will return a 0.

Clears the M3 CPU uncorrectable write error flag.

Figure 5-28. M3 Corrected Error Counter Register (MCECNTR)

M3 CPU/µDMA Corrected Error Counter

In case of an error that has been corrected during M3 CPU or µDMA reads, this counter increments

by 1. After increment, if this counter value becomes equal to the value configured in the MCETRES

Note: Writing a value equal to the MCETRES generates an interrupt and sets the MCEFLG.

RAM Control Module Registers

Internal Memory

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