Cx Shram Configuration Register 2 (Cxsrcr2); Cx Shram Configuration Register 2 (Cxsrcr2) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Table of Contents

Table 5-14. Cx SHRAM Configuration Register 1 (CxSRCR1) Field Descriptions (continued)

Cx SHRAM Config Register 2 (CxSRCR2)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-15. Cx SHRAM Configuration Register 2 (CxSRCR2) Field Descriptions

SPRUHE8E – October 2012 – Revised November 2019

Submit Documentation Feedback

M3 uDMA Write allowed to C2 RAM Block.

M3 uDMA Write not allowed to C2 RAM Block.

M3 CPU Fetch allowed from C2 RAM Block.

M3 CPU Fetch not allowed from C2 RAM Block.

Figure 5-6. Cx SHRAM Configuration Register 2 (CxSRCR2)

M3 CPU Write allowed to C9 RAM Block

M3 CPU Write not allowed to C9 RAM Block.

M3 uDMA Write allowed to C9 RAM Block.

M3 uDMA Write not allowed to C9 RAM Block.

M3 CPU Fetch allowed from C9 RAM Block.

M3 CPU Fetch not allowed from C9 RAM Block.

M3 CPU Write allowed to C8 RAM Block.

M3 CPU Write not allowed to C8 RAM Block.

M3 uDMA Write allowed to C8 RAM Block.

M3 uDMA Write not allowed to C8 RAM Block.

M3 CPU Fetch allowed from C8 RAM Block.

M3 CPU Fetch not allowed from C8 RAM Block.

M3 CPU Write allowed to C7 RAM Block.

M3 CPU Write not allowed to C7 RAM Block.

RAM Control Module Registers

Internal Memory

Chapters

Table of Contents