Control Subsystem Clocks And Low Power Mode Configuration - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Clock Control

Figure 1-12. Control Subsystem Clocks and Low Power Mode Configuration

PIEINTRS (1)

C28x Normal Mode

In normal mode, the C28x processor, most memory, and most of the peripherals are clocked by the

C28SYSCLK, which is derived from the C28CLKIN input clock to the C28x processor. The remainder of

the memories, FPU, VCU, PIE, and three timers are clocked by C28CPUCLK, which is also derived from

the C28CLKIN. Timer 2 can be clocked by TMR2CLK, which is a divided-down version of one of three

source clocks: C28SYSCLK, OSCCLK, or 10 MHZCLK as selected by the CLKCTL register.

Additionally, the LOSPCP register can be programmed to provide a low-speed clock (C28LSPCLK) to the

SCI, SPI, and McBSP peripherals. Clock gating for individual peripherals is defined inside the

PCLKCR0,1, and 3 registers. Execution of the IDLE instruction stops the C28x processor from clocking

and activates the IDLES signal. The IDLES signal is gated with two LPM bits of the CLPMCR0 register to

enter the control subsystem into idle mode or standby mode.

System Control and Interrupts

MASTER SUBSYSTEM

SYSDIVSEL REG

SYSPLLSTAT REG

SYSPLLMULT REG

SYSPLLCTL REG

CCLKREQUEST REG

SELECT QUALIFICATION

SELECT ONE OF 62 GPIs

for more details on these registers.

CLPMSTAT REG

C28x must control pin

(NOTE: IN REVISION 0 OF SILICON, XCLKOUT = PLLSYSCLK DIVIDED DOWN BY 1, 2 OR 4)

execution of IDLE instruction

activates the IDLES signal

SPRUHE8E – October 2012 – Revised November 2019

XPLLCLKCFG REG

XPLLCLKOUTDIV

PIEINTRS (12:1)

TMR2CLKSRCSEL

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