I2C Master Slave Address (I2Cmsa) Register; I2C Master Slave Address (I2Cmsa) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions
22.6 Register Descriptions
The remainder of this section lists and describes the I2S registers, in numerical order by address offset.
22.6.1 I2C Master Slave Address (I2CMSA), offset 0x000
The I2C Master Slave Address (I2CMSA) register consists of eight bits: seven address bits (A6-A0), and a
receive/send bit, which determines if the next operation is a receive (high), or transmit (low). It is shown
and described below.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-3. I2C Master Slave Address (I2CMSA) Register Field Descriptions
Bit Field
31-8 Reserved
7-1 SA
0 R/S
1536
M3 Inter-Integrated Circuit (I2C) Interface
Figure 22-14. I2C Master Slave Address (I2CMSA) Register
R-0
Value Description
Reserved
I2C Slave Address. Specifies bits A6 through A0 of the slave address
0
1
Receive/Send. R/S bit specifies if the next operation is a receive (high) or transmit (low).
0 Transmit
1 Receive
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R-0
8 7
SPRUHE8E – October 2012 – Revised November 2019
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1
SA
R/W-0
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16
0
R/S
R/W-0