C-Boot Rom Ram Initialization; C-Boot Rom Ram Usage - Texas Instruments Concerto F28M36 Series Technical Reference Manual

C-Boot ROM Description
Vector Name (Number)
NMI (18)
ILLEGAL or ITRAP (19)
USER1 (20) – USER12 (31)
PIE-GROUP1
INT1.1 (32) – INT1.8 (39)
PIE-GROUP2
INT2.1 (40) – INT1.8 (47)
PIE-GROUP3
INT3.1 (48) – INT3.8 (55)
PIE-GROUP4
INT4.1 (56) – INT4.8 (63)
PIE-GROUP5
INT5.1 (64) – INT5.8 (71)
PIE-GROUP6
INT6.1 (72) – INT6.8 (79)
PIE-GROUP7
INT7.1 (80) – INT7.8 (87)
PIE-GROUP8
INT8.1 (88) – INT8.8 (95)
PIE-GROUP9
INT9.1 (96) – INT9.8 (103)
PIE-GROUP10
INT10.1 (104) – INT10.8 (111)
PIE-GROUP11
INT11.1 (112)
INT11.2 (113) - INT11.4 (115)
INT11.5 (116)
INT11.6 (117) – INT11.8 (119)
PIE-GROUP12
INT12.1 (120) – INT12.8 (127)

6.6.2 C-Boot ROM RAM Initialization

As mentioned earlier, RAM memories on the master and control subsystems on these devices must be
zero-initialized before using the RAM for the first time to avoid any ECC and Parity errors. Refer to the
Internal Memory chapter for more details on RAM ECC and Parity.
C-Boot ROM zero-initializes all the Control subsystem RAMs as part of the device initialization process if
the POR reset cause bit is set in the CRESC register. For all the other resets, C-Boot ROM stack memory
is zero-initialized. C-Boot ROM actions for possible reset causes are further defined below in this chapter.

6.6.3 C-Boot ROM RAM Usage

The M0 memory block address range 0x0002 - 0x00A0 is reserved for the stack and .ebss code sections
during the bootload process. If code is bootloaded into this region there is no error checking to prevent it
from corrupting the boot ROM stack.
620
ROM Code and Peripheral Booting
Table 6-14. PIE Vector Table in C-Boot ROM (continued)
Vector Address or Location – When PIE
is enabled, during boot process
0x00000D24
0x00000D26
0x00000D28 - 0x00000D3E
0x00000D40 - 0x00000D4E
0x00000D50 - 0x00000D5E
0x00000D60 - 0x00000D6E
0x00000D70 - 0x00000D7E
0x00000D80 - 0x00000D8E
0x00000D90 - 0x00000D9E
0x00000DA0 - 0x00000DAE
0x00000DB0 - 0x00000DBE
0x00000DC0 - 0x00000DCE
0x00000DD0 - 0x00000DDE
0x00000DE0
0x00000DE2 - 0x00000DE6
0x00000DE8
0x00000DEA - 0x00000DEE
0x00000DF0 - 0x00000DFE
Copyright © 2012–2019, Texas Instruments Incorporated
Contents (Handler address)
cbrom_handle_nmi
cbrom_itrap_isr
cbrom_pie_isr_not_supported
cbrom_pie_isr_not_supported
cbrom_pie_isr_not_supported
cbrom_pie_isr_not_supported
cbrom_pie_isr_not_supported
cbrom_pie_isr_not_supported
cbrom_pie_isr_not_supported
cbrom_pie_isr_not_supported
cbrom_pie_isr_not_supported
cbrom_pie_isr_not_supported
cbrom_pie_isr_not_supported
cbrom_mtoc_ipc_int1_isr
cbrom_pie_isr_not_supported
TI-RESERVED
cbrom_pie_isr_not_supported
cbrom_pie_isr_not_supported
SPRUHE8E – October 2012 – Revised November 2019
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