Complete Data Transfer With A 7-Bit Address; R/S Bit In First Byte; Data Validity During Bit Transfer On The I2C Bus - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Functional Description
SDA
SCL
Start
The first seven bits of the first byte make up the slave address (see
determines the direction of the message. A zero in the R/S position of the first byte means that the master
transmits (sends) data to the selected slave, and a 1 (one) in this position means that the master receives
data from the slave.
22.3.1.3 Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can only
change when SCL is Low (see
Figure 22-6. Data Validity During Bit Transfer on the I2C Bus
22.3.1.4 Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During the
acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line. To
acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock cycle. The
data transmitted out by the receiver during the acknowledge cycle must comply with the data validity
requirements described in
When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave so
that the master can generate a STOP condition and abort the current transfer. If the master device is
acting as a receiver during a transfer, it is responsible for acknowledging each transfer made by the slave.
Because the master controls the number of bytes in the transfer, it signals the end of data to the slave
transmitter by not generating an acknowledge on the last data byte. The slave transmitter must then
release SDA to allow the master to generate the STOP or a repeated START condition.
22.3.1.5 Arbitration
A master may start a transfer only if the bus is idle. It is possible for two or more masters to generate a
START condition within minimum hold time of the START condition. In these situations, an arbitration
scheme takes place on the SDA line, while SCL is high. During arbitration, the first of the competing
master devices to place a '1' (high) on SDA while another master transmits a '0' (low) switches off its data
output stage and retires until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if both
masters are trying to address the same device, arbitration continues on to the comparison of data bits.
22.3.2 Available Speed Modes
The I2C bus can run in either standard mode (100 kbps) or fast mode (400 kbps). The selected mode
should match the speed of the other I2C devices on the bus
1524
M3 Inter-Integrated Circuit (I2C) Interface
Figure 22-4. Complete Data Transfer with a 7-Bit Address
MSB LSB R/S
1 2 7 8
Slave add ress
Figure 22-5. R/S Bit in First Byte
MSB
Slave a ddress
Figure 22-6).
SDA
SCL
Dataline
stable
Section 22.3.1.3.
Copyright © 2012–2019, Texas Instruments Incorporated
ACK MSB LSB
9 1 2 7 8
Data
Figure
LSB
R/S
Change
of data
allowed
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
ACK
9
Stop
22-5). The eighth bit
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