Master Subsystem Flash Ecc/Error Log Registers; Ecc Enable Register (Ecc_Enable); Single Error Address Register (Single_Err_Addr); Uncorrectable Error Address Register (Unc_Err_Addr) - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Flash Registers

5.4.2 Master Subsystem Flash ECC/Error Log Registers

5.4.2.1

ECC Enable Register (ECC_Enable)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-103. ECC Enable Register (ECC_Enable) Field Descriptions
Bit Field
31-4 Reserved
3-0 ENABLE
5.4.2.2

Single Error Address Register (SINGLE_ERR_ADDR)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-104. Single Error Address Register (SINGLE_ERR_ADDR) Field Descriptions
Bit Field
31-0 ERR_ADDR
5.4.2.3

Uncorrectable Error Address Register (UNC_ERR_ADDR)

Figure 5-97. Uncorrectable Error Address Register (UNC_ERR_ADDR)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-105. Uncorrectable Error Address Register (UNC_ERR_ADDR) Field Descriptions
Bit Field
31-0 UNC_ERR_ADD
R
560
Internal Memory
Figure 5-95. ECC Enable Register (ECC_Enable)
Reserved
R-0
Value Description
Reserved
0xA ECC enable. A value of 0xA would enable ECC. Any other value would disable ECC.
Figure 5-96. Single Error Address Register (SINGLE_ERR_ADDR)
Value Description
Address at which a single bit error occurred, aligned to a 64-bit boundary.
UNC_ERR_ADDR
Value Description
Address at which an un-correctable error occurred, aligned to a 64-bit boundary
Copyright © 2012–2019, Texas Instruments Incorporated
ERR_ADDR
R-0
R-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
4 3 0
ENABLE
R/W-0xA
0
0
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