Timerxtpr Register (X = 0, 1, 2); Timerxtpr Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Clock Control
Table 1-21. TIMERxTCR Register Field Descriptions (continued)
Bits Field
14 TIE
13-12 Reserved
11-10 FREE
SOFT
9-6 Reserved
5 TRB
4 TSS
3-0 Reserved
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bits Field Description
15-8 PSC CPU-Timer Prescale Counter. These bits hold the current prescale count for the timer. For every timer clock
source cycle that the PSCH:PSC value is greater than 0, the PSCH:PSC decrements by one. One timer clock
(output of the timer prescaler) cycle after the PSCH:PSC reaches 0, the PSCH:PSC is loaded with the contents
of the TDDRH:TDDR, and the timer counter register (TIMH:TIM) decrements by one. The PSCH:PSC is also
reloaded whenever the timer reload bit (TRB) is set by software. The PSCH:PSC can be checked by reading
the register, but it cannot be set directly. It must get its value from the timer divide-down register
(TDDRH:TDDR). At reset, the PSCH:PSC is set to 0.
7-0 TDDR CPU-Timer Divide-Down. Every (TDDRH:TDDR + 1) timer clock source cycles, the timer counter register
(TIMH:TIM) decrements by one. At reset, the TDDRH:TDDR bits are cleared to 0. To increase the overall timer
count by an integer factor, write this factor minus one to the TDDRH:TDDR bits. When the prescaler counter
(PSCH:PSC) value is 0, one timer clock source cycle later, the contents of the TDDRH:TDDR reload the
PSCH:PSC, and the TIMH:TIM decrements by one. TDDRH:TDDR also reloads the PSCH:PSC whenever the
timer reload bit (TRB) is set by software.
140
System Control and Interrupts
Value
CPU-Timer Interrupt Enable.
0 The CPU-Timer interrupt is disabled.
1 The CPU-Timer interrupt is enabled. If the timer decrements to zero, and TIE is set, the
timer asserts its interrupt request.
Reserved
CPU-Timer Emulation Modes: These bits are special emulation bits that determine the
state of the timer when a breakpoint is encountered in the high-level language
debugger. If the FREE bit is set to 1, then, upon a software breakpoint, the timer
continues to run (that is, free runs). In this case, SOFT is a don't care. But if FREE is 0,
then SOFT takes effect. In this case, if SOFT = 0, the timer halts the next time the
TIMH:TIM decrements. If the SOFT bit is 1, then the timer halts when the TIMH:TIM
has decremented to zero.
FREE SOFT CPU-Timer Emulation Mode
0 0 Stop after the next decrement of the TIMH:TIM (hard stop)
0 1 Stop after the TIMH:TIM decrements to 0 (soft stop)
1 0 Free run
1 1 Free run
In the SOFT STOP mode, the timer generates an interrupt before shutting down (since
reaching 0 is the interrupt causing condition).
Reserved
CPU-Timer Reload bit.
0 The TRB bit is always read as zero. Writes of 0 are ignored.
1 When you write a 1 to TRB, the TIMH:TIM is loaded with the value in the PRDH:PRD,
and the prescaler counter (PSCH:PSC) is loaded with the value in the timer divide-
down register (TDDRH:TDDR).
CPU-Timer stop status bit. TSS is a 1-bit flag that stops or starts the CPU-timer.
0 Reads of 0 indicate the CPU-timer is running.
To start or restart the CPU-timer, set TSS to 0. At reset, TSS is cleared to 0 and the
CPU-timer immediately starts.
1 Reads of 1 indicate that the CPU-timer is stopped.
To stop the CPU-timer, set TSS to 1.
Reserved
Figure 1-21. TIMERxTPR Register (x = 0, 1, 2)
PSC
R-0
Table 1-22. TIMERxTPR Register Field Descriptions
Copyright © 2012–2019, Texas Instruments Incorporated
Description
8 7
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
TDDR
R/W-0
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