Spi Fifo Transmit (Spifftx) Register − Address 704Ah; Spi Fifo Receive (Spiffrx) Register − Address 704Bh; Spi Fifo Transmit (Spifftx) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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12.3.1.9 SPI FIFO Transmit, Receive, and Control Registers
Figure 12-21. SPI FIFO Transmit (SPIFFTX) Register − Address 704Ah
15 14
SPIRST SPIFFENA
R/W-1 R/W−0
7 6
TXFFINT Flag TXFFINT CLR
R/W-0 W−0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-17. SPI FIFO Transmit (SPIFFTX) Register Field Descriptions
Bit Field
15 SPIRST
14 SPIFFENA
13 TXFIFO Reset
12-8 TXFFST4−0
7 TXFFINT
6 TXFFINT CLR
5 TXFFIENA
4-0 TXFFIL4−0
Figure 12-22. SPI FIFO Receive (SPIFFRX) Register − Address 704Bh
15 14
RXFFOVF Flag RXFFOVF CLR
R-0 W−0
7 6
RXFFINT Flag RXFFINT CLR
R-0 W−0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUHE8E – October 2012 – Revised November 2019
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13 12
TXFIFO TXFFST4
R/W-1 R−0
5 4
TXFFIENA TXFFIL4
R/W-0 R/W-0
Value Description
SPI reset
0 Write 0 to reset the SPI transmit and receive channels. The SPI FIFO register configuration bits will
be left as is.
1 SPI FIFO can resume transmit or receive. No effect to the SPI registers bits.
SPI FIFO enhancements enable
0 SPI FIFO enhancements are disabled
1 SPI FIFO enhancements are enabled
Transmit FIFO reset
0 Write 0 to reset the FIFO pointer to zero, and hold in reset.
1 Re-enable Transmit FIFO operation
Transmit FIFO status
00000 Transmit FIFO is empty.
00001 Transmit FIFO has 1 word.
00010 Transmit FIFO has 2 words.
00011 Transmit FIFO has 3 words.
00100 Transmit FIFO has 4words, the maximum
TXFIFO interrupt
0 TXFIFO interrupt has not occurred, This is a read-only bit.
1 TXFIFO interrupt has occurred, This is a read-only bit.
TXFIFO clear
0 Write 0 has no effect on TXFFINT flag bit, Bit reads back a zero.
1 Write 1 to clear TXFFINT flag in bit 7.
TX FIFO interrupt enable
0 TX FIFO interrupt based on TXFFIL match (less than or equal to) will be disabled .
1 TX FIFO interrupt based on TXFFIL match (less than or equal to) will be enabled.
TXFFIL4−0 transmit FIFO interrupt level bits. Transmit FIFO will generate interrupt when the FIFO
status bits (TXFFST4−0) and FIFO level bits (TXFFIL4−0 ) match (less than or equal to).
00000 Default value is 0x00000.
13 12
RXFIFO Reset RXFFST4
R/W−1 R−0
5 4
RXFFIENA RXFFIL4
R/W−0 R/W−1
Copyright © 2012–2019, Texas Instruments Incorporated
11 10
TXFFST3 TXFFST2
R−0 R−0
3 2
TXFFIL3 TXFFIL2
R/W-0 R/W-0
11 10
RXFFST3 RXFFST2
R−0 R−0
3 2
RXFFIL3 RXFFIL2
R/W−1 R/W−1
C28 Serial Peripheral Interface (SPI)
SPI Registers and Waveforms
9 8
TXFFST1 TXFFST0
R−0 R−0
1 0
TXFFIL1 TXFFIL0
R/W-0 R/W-0
9 8
RXFFST1 RXFFST0
R−0 R−0
1 0
RXFFIL1 RXFFIL0
R/W−1 R/W−1
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