Run Mode Clock Configuration (Rcc) Register; Master Gpio High Performance Bus Control (Gpiohbctl) Register; Bit Clock Source Selection For Can1 (Can1Bclksel) Register Field Descriptions; Run Mode Clock Configuration (Rcc) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 1-116. Bit Clock Source Selection for CAN1 (CAN1BCLKSEL) Register Field Descriptions
Bit Field
31-2 Reserved
1-0 BCLKSEL

1.13.7.11 Run Mode Clock Configuration (RCC) Register

31 28 27 26
Reserved ACG
R-0:0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-117. Run Mode Clock Configuration (RCC) Register Field Descriptions
Bit Field
31-28 Reserved
27 ACG
26-0 Reserved

1.13.7.12 Master GPIO High Performance Bus Control (GPIOHBCTL) Register

Figure 1-107. Master GPIO High Performance Bus Control (GPIOHBCTL) Register
31
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-118. Master GPIO High Performance Bus Control (GPIOHBCTL) Register Field Descriptions
Bit Field
31-9 Reserved
8 PORT J
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
Reserved
Bit Clock Source Select
00 CAN1 bit clock = M3 SS_CLK
01 CAN1 bit clock = OSCCLK
1x CAN1 bit clock = GPIO_XCLKIN
Figure 1-106. Run Mode Clock Configuration (RCC) Register
Value Description
Reserved
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCx) registers
and Deep-Sleep-Mode Clock Gating Control (DCGC) registers if the M3 CPU enters a sleep or
deep-sleep mode.
The RCGC registers are always used to control the clocks in run mode.
0 The Run-Mode Clock Gating Control (RCGCx) registers are used when the microcontroller enters a
sleep mode.
1 The SCGCx or DCGCx registers are used to control the clocks distributed to the peripherals when
the microcontroller is in a sleep mode. The SCGCx and DCGCx registers allow unused peripherals
to consume less power when the M3 CPU in a sleep mode.
Reserved
9
R/W-0
Value Description
Reserved
PORT J AHB. This bit defines the memory aperture for Port J
0 Advanced Peripheral Bus (APB). This bus is the legacy bus.
1 Advanced High-Performance Bus (AHB)
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0:0
Reserved
R-0
8 7 6 5
PORT PORT PORT PORT
J H G F
R/W-0 R/W-0 R/W-0
System Control Registers
4 3 2 1
PORT PORT PORT PORT
E D C B
R/W-0 R/W-0 R/W-0 R/W-0
System Control and Interrupts
0
16
0
PORT
A
R/W-0
231