Reserved Locations Within Flash And Otp - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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• The FECC_OUTH register holds the data output bits 63:32 from the SECDED block under test
• The FECC_OUTL register holds the data output bits 31:0 from the SECDED block under test
• The FECC_STATUS register holds the status of single-bit error occurrence, uncorrectable error
occurrence, and error position of single bit error in data/check bits

5.3.11 Reserved Locations Within Flash and OTP

When allocating code and data to flash and OTP memory, keep the following reserved locations of
flash/OTP in mind:
• M3 OTP has reserved locations for OTPSECLOCK, Zone 2 Flash entry point, EMAC ID, and Main
Oscillator Clock frequency whose address locations and sizes are mentioned earlier. For more details
on the functionality of these fields, please refer to the System Control and Interrupts chapter and the
ROM Code and Peripheral Booting chapter.
• Refer to the Code Security Module (CSM) section in the System control and Interrupts chapter for
reserved locations in M3 flash for Zone 1 and Zone 2 CSM password, Zone 1 and Zone 2 ECSL
passwords, Zone 1 and Zone 2 GRABSECT, GRABRAM, and EXEONLY fields.
• Refer to the CSM section in the System Control and Interrupts chapter for reserved locations in C28x
flash for CSM password, ECSL password, and EXEONLY field.
• Refer to the ROM Code and Peripheral Booting chapter for reserved locations in M3 flash and C28x
flash for boot to flash entry point. These locations are reserved for an entry into flash branch
instruction. When the boot to flash boot option is used, the boot ROM will jump to these addresses in
flash. If the user programs a branch instruction here, that will then re-direct code execution to the entry
point of the application.
• For code security operation, all address ranges (inclusive) given below in M3 Flash cannot be used for
program code or data, but must be programmed to 0x00 when the Code Security Password is
programmed in M3 Flash. If security is not a concern, then these addresses may be used for code or
data. See the System Control and Interrupts chapter for information in using the CSM.
– From 0x00200024 to 0x0020002F
– From 0x00200050 to 0x00200 1FF
– From 0x002FFE00 to 0x002FFFDB
• For code security operation, all addresses from 0x0013FF80 to 0x0013FFEF (inclusive of these
addresses) in C28x Flash cannot be used for program code or data, but must be programmed to
0x0000 when the Code Security Password is programmed in C28x Flash. If security is not a concern,
then these addresses may be used for code or data. See the System Control and Interrupts chapter for
information on using the CSM.
5.3.12 Procedure to Change the Flash Control Registers
During flash configuration, no accesses to the flash or OTP can be in progress. This includes instructions
still in the CPU pipeline, data reads, and instruction prefetch operations. To be sure that no access takes
place during the configuration change, you should follow the procedure shown below for any code that
modifies the flash control registers. This is applicable for both master subsystem and control subsystem
application.
1. Start executing application code from RAM/Flash/OTP.
2. Branch to or call the flash configuration code (that writes to flash control registers) in RAM. This is
required to properly flush the CPU pipeline before the configuration change. (The function that changes
the flash configuration cannot execute from the flash or OTP. It must reside in RAM .
3. Execute the Flash configuration code (should be located in RAM) that writes to flash control registers
like FRDCNTL, FRD_INTF_CTRL etc.
4. At the end of the flash configuration code execution, wait eight cycles to let the write instructions
propagate through the CPU pipeline. This must be done before the return-from-function call is made.
5. Return to the calling function which might reside in RAM or Flash/OTP and continue execution.
SPRUHE8E – October 2012 – Revised November 2019
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Flash Controller Memory Module
Internal Memory
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