Configuring A Peripheral For Ping-Pong Receive; Primary And Alternate Channel Control Structure Offsets For Channel 8 - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Initialization and Configuration
NOTE: In this example, it is not important if the peripheral makes a single request or a burst request.
Because the peripheral has a FIFO that triggers at a level of 4, the arbitration size is set to 4.
If the peripheral does make a burst request, then 4 bytes are transferred, which is what the
FIFO can accommodate. If the peripheral makes a single request (if there is any space in the
FIFO), then one byte is transferred at a time. If it is important to the application that transfers
only be made in bursts, then the Channel Useburst SET[7] bit should be set in the DMA
Channel Useburst Set (DMAUSEBURSTSET) register.
16.4.3.3 Start the Transfer
Now the channel is configured and is ready to start.
Enable the channel by setting bit 7 of the DMA Channel Enable Set (DMAENASET) register.
The µDMA controller is now configured for transfer on channel 7. The controller makes transfers to the
peripheral whenever the peripheral asserts a µDMA request. The transfers continue until the entire buffer
of 64 bytes has been transferred. When that happens, the µDMA controller disables the channel and sets
the XFERMODE field of the channel control word to 0 (Stopped). The status of the transfer can be
checked by reading bit 7 of the DMA Channel Enable Set (DMAENASET) register. This bit is automatically
cleared when the transfer is complete. The status can also be checked by reading the XFERMODE field of
the channel control word at offset 0x078. This field is automatically cleared at the end of the transfer.
If peripheral interrupts are enabled, then the peripheral interrupt handler receives an interrupt when the
entire transfer is complete.

16.4.4 Configuring a Peripheral for Ping-Pong Receive

This example configures the µDMA controller to continuously receive 8-bit data from a peripheral into a
pair of 64-byte buffers. The peripheral has a receive FIFO with a trigger level of 8. The example peripheral
uses µDMA channel 8.
16.4.4.1 Configure the Channel Attributes
First, configure the channel attributes:
• Configure bit 8 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear
(DMAPRIOCLR) registers to set the channel to High priority or Default priority.
• Set bit 8 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the primary
channel control structure for this transfer.
• Set bit 8 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the µDMA
controller to respond to single and burst requests.
• Set bit 8 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow the µDMA
controller to recognize requests for this channel.
16.4.4.2 Configure the Channel Control Structure
This example transfers bytes from the peripheral's receive FIFO register into two memory buffers of 64
bytes each. As data is received, when one buffer is full, the µDMA controller switches to use the other.
To use Ping-Pong buffering, both primary and alternate channel control structures must be used. The
primary control structure for channel 8 is at offset 0x080 of the channel control table, and the alternate
channel control structure is at offset 0x280. The channel control structures for channel 8 are located at the
offsets shown in Table
Table 16-11. Primary and Alternate Channel Control Structure Offsets for Channel 8
Control Table Base + 0x080
Control Table Base + 0x084
1204
M3 Micro Direct Memory Access ( µDMA)
16-11.
Offset
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Description
Channel 8 Primary Source End Pointer
Channel 8 Primary Destination End Pointer
SPRUHE8E – October 2012 – Revised November 2019
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