Memory Management Fault Address (Mmaddr) Register; Bus Fault Address (Faultaddr) Register Register; Memory Management Fault Address (Mmaddr) Register Field Descriptions; Bus Fault Address (Faultaddr) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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25.6.14 Memory Management Fault Address (MMADDR) Register, offset 0xD34
The Memory Management Fault Address (MMADDR) register contains the address of the location that
generated a memory management fault. When an unaligned access faults, the address in the MMADDR
register is the actual address that faulted. Because a single read or write instruction can be split into
multiple aligned accesses, the fault address can be any address in the range of the requested access
size. Bits in the Memory Management Fault Status (MFAULTSTAT) register indicate the cause of the fault
and whether the value in the MMADDR register is valid.
Note: This register can only be accessed from privileged mode.
Figure 25-45. Memory Management Fault Address (MMADDR) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-52. Memory Management Fault Address (MMADDR) Register Field Descriptions
Bit Field
31 ADDR
25.6.15 Bus Fault Address (FAULTADDR) Register, offset 0xD38
The Bus Fault Address (FAULTADDR) register contains the address of the location that generated a bus
fault. When an unaligned access faults, the address in the FAULTADDR register is the one requested by
the instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT)
register indicate the cause of the fault and whether the value in the FAULTADDR register is valid.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-53. Bus Fault Address (FAULTADDR) Register Field Descriptions
Bit Field
31 ADDR
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
Fault Address
When the MMARV bit of MFAULTSTAT is set, this field holds the address of the location that
generated the memory management fault.
Figure 25-46. Bus Fault Address (FAULTADDR) Register Register
Value Description
Fault Address
When the MMARV bit of MFAULTSTAT is set, this field holds the address of the location that
generated the memory management fault.
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System Control Block (SCB) Register Descriptions
ADDR
R/W
ADDR
R/W
0
0
1685
Cortex-M3 Peripherals