Gpio Port E Qualification Select 1 (Gpeqsel1) Register; Gpio Port A Direction (Gpadir) Register; Gpio Port E Qualification Select 1 (Gpeqsel1) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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4.2.7.29 GPIO Port E Qualification Select 1 (GPEQSEL1) Register

The GPIO Port E Qualification Select 1 (GPEQSEL1) register is shown and described in the figure and
table below.
Figure 4-70. GPIO Port E Qualification Select 1 (GPEQSEL1) Register
31
15 14 13 12
GPIO135 GPIO134
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-79. GPIO Port E Qualification Select 1 (GPEQSEL1) Register Field Descriptions
Bits Field
31-16 Reserved
15-0 GPIO135-GPIO128
(1)
This register is EALLOW protected.
The GPxDIR registers control the direction of the pins when they are configured as a GPIO in the
appropriate MUX register. The direction register has no effect on pins configured as peripheral functions.

4.2.7.30 GPIO Port A Direction (GPADIR) Register

The GPIO Port A Direction (GPADIR) register is shown and described in the figure and table below.
31 30
GPIO31 GPIO30
R/W-0 R/W-0
23 22
GPIO23 GPIO22
R/W-0 R/W-0
15 14
GPIO15 GPIO14
R/W-0 R/W-0
7 6
GPIO7 GPIO6
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUHE8E – October 2012 – Revised November 2019
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Reserved
R-0
11 10 9 8
GPIO133 GPIO132
R/W-0 R/W-0
Value
Any writes to these bit(s) must always have a value of 0.
Select input qualification type for GPIO128 to GPIO135 . The input qualification of each
GPIO input is controlled by two bits.
00 Synchronize to analog subsystem clock. Valid for both peripheral and GPIO pins.
01 Qualification using 3 samples. Valid for pins configured as GPIO or a peripheral function.
The time between samples is specified in the GPECTRL register.
10 Qualification using 6 samples. Valid for pins configured as GPIO or a peripheral function.
The time between samples is specified in the GPECTRL register.
11 Asynchronous. (no synchronization or qualification). This option applies to pins configured
as peripherals only. If the pin is configured as a GPIO input, then this option is the same as
0,0 or synchronize to analog subsystem clock.
Figure 4-71. GPIO Port A Direction (GPADIR) Register
29 28
GPIO29 GPIO28
R/W-0 R/W-0
21 20
GPIO21 GPIO20
R/W-0 R/W-0
13 12
GPIO13 GPIO12
R/W-0 R/W-0
5 4
GPIO5 GPIO4
R/W-0 R/W-0
Copyright © 2012–2019, Texas Instruments Incorporated
C28 General-Purpose Input/Output (GPIO)
7 6 5 4
GPIO131 GPIO130
R/W-0 R/W-0
(1)
Description
27 26
GPIO27 GPIO26
R/W-0 R/W-0
19 18
GPIO19 GPIO18
R/W-0 R/W-0
11 10
GPIO11 GPIO10
R/W-0 R/W-0
3 2
GPIO3 GPIO2
R/W-0 R/W-0
General-Purpose Input/Output (GPIO)
16
3 2 1 0
GPIO129 GPIO128
R/W-0 R/W-0
25 24
GPIO25 GPIO24
R/W-0 R/W-0
17 16
GPIO17 GPIO16
R/W-0 R/W-0
9 8
GPIO9 GPIO8
R/W-0 R/W-0
1 0
GPIO1 GPIO0
R/W-0 R/W-0
441