Simplified Acib Model; Simplified Acib Signals - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Analog
ADC
COMP
Signal
Clock
Bus[7:0]
Size
R/W
All ACIB activity operates at a frequency equal to the analog subsystem clock rate. Register accesses
across the ACIB are handled as data read and write operations. Trigger and interrupt signals are specially
encoded by the ACIB for lower latency behavior.
ACIB buffers on both the digital and analog subsystems act as an intermediary translation stage for any
information that is transmitted and received across the bus. This translation stage will introduce latency
beyond the time required for bus activity alone.
The translation latency is represented by the digital buffer and analog buffer signals in
Figure 10-9. The digital and analog subsystems are not able to use the information received across the
ACIB bus until the respective buffer signal has de-asserted.
While the buffers are busy, a synchronization stall is active whenever the ACIB bus is not carrying data.
For communications originating from the digital subsystem, there can be one cycle of jitter during the
opening synchronization sequence.
Read and write operations are processed in the order in which they are received, but they will be
preempted in place by ADC trigger and interrupt signals in case of contention. For instances where
operations are pending from multiple CPU or DMA sources, the transactions are processed in a round-
robin manner.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 10-2. Simplified ACIB Model
ACIB
Clock
B
u
Bus[7:0]
f
f
Size
e
R/W
r
Table 10-1. Simplified ACIB Signals
Direction
Analog to Digital
Bidirectional
Digital to Analog
Digital to Analog
Copyright © 2012–2019, Texas Instruments Incorporated
Analog Common Interface Bus (ACIB)
Digital
B
Master
u
f
f
e
Control
r
Description
ACIB clock
General purpose bus that carries address,
data, trigger, and interrupt information.
Size of the requested read or write
operation. The Size signal can only
request 16-bit or 32-bit data operations.
A burst read of 64-bits is automatically
initiated by requesting a 32-bit read on an
address that is aligned to a 64-bit
boundary -- there is no way to disable
burst reads.
Burst writes are not supported.
Type of data operation. Read or write, with
respect to the Digital subsystem.
Figure 10-3
Analog Subsystem
to
893