Spi Status Register (Spist) - Address 7042H; Spi Status Register (Spist) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 12-10. SPI Operation Control Register (SPICTL) Field Descriptions (continued)
Bit Field
1 TALK
0 SPI INT ENA
12.3.1.3 SPI Status Register (SPIST)
7 6
RECEIVER SPI INT
(1) (2)
OVERRUN FLAG
(1) (2)
FLAG
R/C-0 R/C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
The RECEIVER OVERRUN FLAG bit and the SPI INT FLAG bit share the same interrupt vector.
(2)
Writing a 0 to bits 5, 6, and 7 has no effect.
Bit Field
7 RECEIVER
OVERRUN FLAG
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
Master/Slave Transmit Enable. The TALK bit can disable data transmission (master or slave) by
placing the serial data output in the high-impedance state. If this bit is disabled during a
transmission, the transmit shift register continues to operate until the previous character is shifted
out. When the TALK bit is disabled, the SPI is still able to receive characters and update the status
flags. TALK is cleared (disabled) by a system reset.
0 Disables transmission:
• Slave mode operation: If not previously configured as a general-purpose I/O pin, the SPISOMI
pin will be put in the high-impedance state.
• Master mode operation: If not previously configured as a general-purpose I/O pin, the SPISIMO
pin will be put in the high-impedance state.
1 Enables transmission For the 4-pin option, ensure to enable the receiver's SPISTE input pin.
SPI Interrupt Enable. This bit controls the SPI's ability to generate a transmit/receive interrupt. The
SPI INT FLAG bit (SPISTS.6) is unaffected by this bit.
0 Disables interrupt
1 Enables interrupt
Figure 12-15. SPI Status Register (SPIST) — Address 7042h
5 4
TX BUF FULL
(2)
FLAG
R/C-0
Table 12-11. SPI Status Register (SPIST) Field Descriptions
Value Description
SPI Receiver Overrun Flag. This bit is a read/clear-only flag. The SPI hardware sets this bit when a
receive or transmit operation completes before the previous character has been read from the
buffer. The bit indicates that the last received character has been overwritten and therefore lost
(when the SPIRXBUF was overwritten by the SPI module before the previous character was read
by the user application). The SPI requests one interrupt sequence each time this bit is set if the
OVERRUN INT ENA bit (SPICTL.4) is set high. The bit is cleared in one of three ways:
• Writing a 1 to this bit
• Writing a 0 to SPI SW RESET (SPICCR.7)
• Resetting the system
If the OVERRUN INT ENA bit (SPICTL.4) is set, the SPI requests only one interrupt upon the first
occurrence of setting the RECEIVER OVERRUN Flag bit. Subsequent overruns will not request
additional interrupts if this flag bit is already set. This means that in order to allow new overrun
interrupt requests the user must clear this flag bit by writing a 1 to SPISTS.7 each time an overrun
condition occurs. In other words, if the RECEIVER OVERRUN Flag bit is left set (not cleared) by
the interrupt service routine, another overrun interrupt will not be immediately re-entered when the
interrupt service routine is exited.
0 Writing a 0 has no effect
1 Clears this bit. The RECEIVER OVERRUN Flag bit should be cleared during the interrupt service
routine because the RECEIVER OVERRUN Flag bit and SPI INT FLAG bit (SPISTS.6) share the
same interrupt vector. This will alleviate any possible doubt as to the source of the interrupt when
the next byte is received.
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SPI Registers and Waveforms
Reserved
R-0
C28 Serial Peripheral Interface (SPI)
0
1003