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Texas Instruments TMS570LC4357 Technical Reference Manual

Texas Instruments TMS570LC4357 Technical Reference Manual

Tms570lc43 series 16/32-bit risc flash microcontrollers

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TMS570LC43x 16/32-Bit RISC Flash

Microcontroller

Technical Reference Manual

Literature Number: SPNU563A

March 2018

Table of Contents

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biy

May 15, 2025

what shall ichoose in field 'connection while using CCS for my TMS570LC4357

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1 comments:

Mr. Anderson

May 22, 2025

The 'connection' field in CCS for the Texas Instruments TMS570LC4357 should be set to XDS110 debugger.

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Summary of Contents for Texas Instruments TMS570LC4357

Page 1 TMS570LC43x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual Literature Number: SPNU563A March 2018...
Page 2: Table Of Contents
....................3.2.3 SCM Control Block ......................How to Use SCM ..............3.3.1 How to Check the Parity Compare Logic ................3.3.2 How to Initiate Self-test Sequence Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 3 Logic Power Domain Control Register (LOGICPDPWRCTRL0) .......... 5.4.2 Logic Power Domain Control Register (LOGICPDPWRCTRL1) ..........5.4.3 Power Domain Clock Disable Register (PDCLKDISREG) ........5.4.4 Power Domain Clock Disable Set Register (PDCLKDISSETREG) SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 4 ........6.7.14 PINMMRnn: Special Functionality Multiplexing Control Registers ..............F021 Level 2 Flash Module Controller (L2FMC) ........................Overview ......................7.1.1 Features ....................7.1.2 Definition of Terms Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 5 7.10.27 Crossbar Access Time Threshold Register (ACC_THRESHOLD) ....7.10.28 Flash Error Detection and Correction Sector Disable Register 2 (FEDACSDIS2) ........7.10.29 Lower Word of Reset Configuration Read Register (RCR_VALUE0) SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 6 Fail Status Count Registers (FSRC0 and FSRC1) ............9.5.8 Fail Status Address Registers (FSRA0 and FSRA1) ............9.5.9 Fail Status Data Registers (FSRDL0 and FSRDL1) ................... 9.5.10 ROM Mask Register (ROM) Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 7 ..............11.3.1 How to Use NMPU in Functional Mode ..................11.3.2 How to Use Diagnostics ......................11.4 NMPU Registers ............... 11.4.1 MPU Revision ID Register (MPUREV) SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 8 13.3.8 CCM-R5F Status Register 4 (CCMSR4) ..............13.3.9 CCM-R5F Key Register 4 (CCMKEYR4) ......... 13.3.10 CCM-R5F Power Domain Status Register 0 (CCMPDSTAT0) ......................Oscillator and PLL Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 9 15.4.9 DCC Counter1 Value Register (DCCCNT1) ......15.4.10 DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) ......15.4.11 DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) .................... Error Signaling Module (ESM) SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 10 17.2.5 Digital Watchdog (DWD) ....................17.2.6 Low Power Modes ................17.2.7 Halting Debug Mode Behaviour ....................17.3 RTI Control Registers ..............17.3.1 RTI Global Control Register (RTIGCTRL) Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 11 ..................... 18.2.6 Raw Data Register ................18.2.7 Example DMA Controller Setup ..................18.2.8 Pattern Count Register ............18.2.9 Sector Count Register/Current Sector Register ......................18.2.10 Interrupt SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 12 19.3.2 Interrupt Handling at the CPU ................. 19.3.3 Software Interrupt Handling Options ................... 19.4 Interrupt Handling Inside VIM ................19.4.1 VIM Interrupt Channel Mapping ................19.4.2 VIM Input Channel Management Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 13 ....................20.2.14 Request Polarity .................... 20.2.15 Memory Protection ....................20.2.16 ECC Checking ....................20.2.17 ECC Testing ..................20.2.18 Initializing RAM with ECC .................... 20.2.19 Transaction Errors SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 14 ............... 22.2.5 ADC Magnitude Threshold Interrupts .................... 22.2.6 ADC Special Modes ................ 22.2.7 ADC Results’ RAM Special Features ............. 22.2.8 ADEVT Pin General Purpose I/O Functionality Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 15 22.3.50 ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) ....22.3.51 ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) ......22.3.52 ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 16 N2HET Control Registers 1017 ..............23.4.1 Global Configuration Register (HETGCR) 1018 ............... 23.4.2 Prescale Factor Register (HETPFR) 1020 ............23.4.3 N2HET Current Address Register (HETADDR) 1021 Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 17 ............... 23.5.19 HWAG Filter Register 2 (HWAFIL2) 1058 ............23.5.20 HWAG Angle Increment Register (HWAANGI) 1059 ......................23.6 Instruction Set 1060 ..................23.6.1 Instruction Summary 1060 SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 18 24.5.5 Current Full Address A Register (HTU CFADDRA) 1178 ............24.5.6 Current Full Address B Register (HTU CFADDRB) 1179 ............24.5.7 Current Frame Count Register (HTU CFCOUNT) 1180 Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 19 1243 ....................26.2.9 Transmit Process 1246 ..................... 26.2.10 Receive Process 1248 ....................26.2.11 FIFO Function 1249 ................... 26.2.12 Message Handling 1250 ....................26.2.13 Module RAMs 1258 SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 20 27.8.7 Reception of Data Frames 1440 ................27.8.8 Reception of Remote Frames 1440 ................27.8.9 Reading Received Messages 1440 ............. 27.8.10 Requesting New Data for a Receive Object 1441 Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 21 27.17.23 IF1/IF2 Command Registers (DCAN IF1CMD, DCAN IF2CMD) 1478 ........... 27.17.24 IF1/IF2 Mask Registers (DCAN IF1MSK, DCAN IF2MSK) 1481 ........27.17.25 IF1/IF2 Arbitration Registers (DCAN IF1ARB, DCAN IF2ARB) 1482 SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 22 28.3.22 Interrupt Vector 0 (INTVECT0) 1568 ................28.3.23 Interrupt Vector 1 (INTVECT1) 1569 ..............28.3.24 SPI Pin Control Register 9 (SPIPC9) 1571 ..........28.3.25 Parallel/Modulo Mode Control Register (SPIPMCTRL) 1572 Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 23 1641 ......................... 29.3 1642 ................29.3.1 LIN Communication Formats 1642 ....................29.3.2 LIN Interrupts 1659 .................... 29.3.3 LIN DMA Interface 1659 .................... 29.3.4 LIN Configurations 1660 SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 24 30.2.1 SCI Frame Formats 1720 ....................30.2.2 SCI Timing Mode 1721 ....................30.2.3 SCI Baud Rate 1722 ............... 30.2.4 SCI Multiprocessor Communication Modes 1722 ......................30.3 SCI Interrupts 1725 Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 25 I2C Module Data Validity 1770 ..............31.2.4 I2C Module Start and Stop Conditions 1771 ................... 31.2.5 Serial Data Formats 1771 ..................31.2.6 NACK Bit Generation 1773 SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 26 1802 ......................EMAC/MDIO Module 1803 ....................... 32.1 Introduction 1804 ..................32.1.1 Purpose of the Peripheral 1804 ......................32.1.2 Features 1804 ..................32.1.3 Functional Block Diagram 1805 Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 27 32.4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) 1879 ....................32.5 EMAC Module Registers 1880 ..............32.5.1 Transmit Revision ID Register (TXREVID) 1883 ..............32.5.2 Transmit Control Register (TXCONTROL) 1883 SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 28 32.5.50 Network Statistics Registers 1918 ..................Enhanced Capture (eCAP) Module 1927 ....................... 33.1 Introduction 1928 ......................33.1.1 Features 1928 ..................... 33.1.2 Description 1928 ......................33.2 Basic Operation 1929 Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 29 34.3.19 eQEP Interrupt Clear Register (QCLR) 1991 ..............34.3.20 eQEP Capture Timer Register (QCTMR) 1992 ................. 34.3.21 eQEP Status Register (QEPSTS) 1993 ............ 34.3.22 eQEP Capture Timer Latch Register (QCTMRLAT) 1994 SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 30 36.3.7 DMM Interrupt Offset 2 Register (DMMOFF2) 2134 ........36.3.8 DMM Direct Data Mode Destination Register (DMMDDMDEST) 2135 ..........36.3.9 DMM Direct Data Mode Blocksize Register (DMMDDMBL) 2135 Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 31 38.3.1 eFuse Controller Connections to ESM 2188 ..............38.3.2 Checking for eFuse Errors After Power Up 2188 ..................... 38.4 eFuse Controller Registers 2191 ............38.4.1 EFC Boundary Control Register (EFCBOUND) 2191 SPNU563A – March 2018 Contents Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 32 38.4.3 EFC Error Status Register (EFCERRSTAT) 2194 ............... 38.4.4 EFC Self Test Cycles Register (EFCSTCY) 2194 ............38.4.5 EFC Self Test Signature Register (EFCSTSIG) 2195 ........................Revision History 2196 Contents SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 33 ........... 2-44. System Software Interrupt Request 3 Register (SSIR3) (offset = B8h) ........... 2-45. System Software Interrupt Request 4 Register (SSIR4) (offset = BCh) SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 34 2-92. Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0) (offset = A0h) ........2-93. Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) (offset = A4h) ........2-94. Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) (offset = A8h) List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 35 ....... 5-6. Power Domain Clock Disable Set Register (PDCLKDISSETREG) (offset = 24h) ......5-7. Power Domain Clock Disable Clear Register (PDCLKDISCLRREG) (offset = 28h) SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 36 7-14. Flash Port A Error and Status Register (FEDAC_PASTATUS) (offset = 14h) ........7-15. Flash Port B Error and Status Register (FEDAC_PBSTATUS) (offset = 18h) List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 37 ....... 8-11. L2RAMW Bank to Domain Mapping Register1 (BANK_DOMAIN_MAP1) (offset = 48h) ....................9-1. PBIST Block Diagram ................9-2. PBIST Memory Self-Test Flow Diagram SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 38 11-5. MPU Lock Register (MPULOCK) [offset = 04h] ..........11-6. MPU Diagnostics Control Register (MPUDIAGCTRL) [offset = 08h] ..........11-7. MPU Diagnostic Address Register (MPUDIAGADDR) [offset = 0Ch] List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 39 15-4. Clock1 Faster Than Clock0 - Results in an Error and Stops Counting ............. 15-5. Clock1 Not Present - Results in an Error and Stops Counting SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 40 ......... 16-36. ESM Interrupt Enable Set/Status Register 7 (ESMIESR7) [offset = 88h] ........16-37. ESM Interrupt Enable Clear/Status Register 7 (ESMIECR7) [offset = 8Ch] List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 41 ....... 17-45. Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) [offset = A8h] ......17-46. RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) [offset = ACh] SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 42 ............... 19-1. Block Diagram of Dual VIM for Safety Support ................. 19-2. Device Level Interrupt Block Diagram ................. 19-3. VIM Interrupt Handling Block Diagram List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 43 20-3. Example of a DMA Transfer Using Block Trigger Source ............20-4. DMA Request Mapping and Control Packet Organization ..............20-5. Control Packet Organization and Memory Map ....................20-6. DMA Transfer Example 1 SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 44 20-53. BTC Interrupt Enable Set Register (BTCINTENAS) [offset = 10Ch] ..........20-54. BTC Interrupt Enable Reset Register (BTCINTENAR) [offset = 114h] ............20-55. Global Interrupt Flag Register (GINTFLAG) [offset = 11Ch] List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 45 20-102. DMA ECC Single-Bit Error Address Register (DMAECCSBE) [offset = 230h] ............. 20-103. FIFO A Status Register (FIFOASTAT) [offset = 240h] ............. 20-104. FIFO B Status Register (FIFOBSTAT) [offset = 244h] SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 46 21-33. LH28F800BJE-PTTL90 to EMIF Write Timing Waveforms ........21-34. Asynchronous m Configuration Register (m = 1, 2) (CEnCFG (n = 2, 3)) ................22-1. Channel Assignments of Two ADC Cores List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 47 22-48. ADC Group1 Sampling Time Configuration Register (ADG1SAMP) [offset = 64h] ......22-49. ADC Group2 Sampling Time Configuration Register (ADG2SAMP) [offset = 68h] ............22-50. ADC Event Group Status Register (ADEVSR) [offset = 6Ch] SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 48 22-97. ADC Parity Control Register (ADPARCR) [offset = 180h] ..........22-98. ADC Parity Error Address Register (ADPARADDR) [offset = 184h] ......... 22-99. ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) [offset = 188h] List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 49 23-36. Hardware Angle Generator Block Diagram ..................23-37. Angle Tick Generation Principle ................23-38. New Angle Tick Generation Architecture ..............23-39. Angle Generation Using Time Based Algorithm SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 50 23-86. Loop Back Pair Select Register (HETLBPSEL) 1041 ..............23-87. Loop Back Pair Direction Register (HETLBPDIR) 1042 ................23-88. N2HET Pin Disable Register (HETPINDIS) 1043 List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 51 23-134. CNT Program Field (P31:P0) 1086 ..................23-135. CNT Control Field (C31:C0) 1086 ..................... 23-136. CNT Data Field (D31:D0) 1086 ................... 23-137. DADM64 Program Field (P31:P0) 1090 SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 52 23-183. SHFT Program Field (P31:P0) 1124 ..................23-184. SHFT Control Field (C31:C0) 1124 ................... 23-185. SHFT Data Field (D31:D0) 1124 ..................23-186. WCAP Program Field (P31:P0) 1127 List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 53 24-42. Initial Full Address A Register (HTU IFADDRA) 1175 ..............24-43. Initial Full Address B Register (HTU IFADDRB) 1175 ..........24-44. Initial N2HET Address and Control Register (HTU IHADDRCT) 1176 SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 54 26-19. Swapping of IBCM and IBCR Bits 1253 ................26-20. Double Buffer Structure Output Buffer 1255 .................. 26-21. Swapping of OBCM and OBCR Bits 1255 List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 55 26-69. Trigger Transfer to Communication Controller Reset 2 (TTCCR2) [offset_TU = ACh] 1304 ......26-70. Trigger Transfer to Communication Controller Set 3 (TTCCS3) [offset_TU = B0h] 1305 SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 56 26-117. Error Interrupt Register (EIR) [offset_CC = 20h] 1341 ..............26-118. Status Interrupt Register (SIR) [offset_CC = 24h] 1343 ........... 26-119. Error Interrupt Line Select Register (EILS) [offset_CC = 28h] 1346 List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 57 26-166. Transmission Request Register 4 (TXRQ4) [offset_CC = 32Ch] 1396 ..........26-167. Transmission Request Register 3 (TXRQ3) [offset_CC = 328h] 1396 ..........26-168. Transmission Request Register 2 (TXRQ2) [offset_CC = 324h] 1396 SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 58 27-23. Bit Timing Register (DCAN BTR) [offset = 0Ch] 1462 ................ 27-24. Interrupt Register (DCAN INT) [offset = 10h] 1463 ................27-25. Test Register (DCAN TEST) [offset = 14h] 1464 List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 59 ............. 27-73. IF3 Data A Register (DCAN IF3DATA) [offset = 150h] 1492 ............. 27-74. IF3 Data B Register (DCAN IF3DATB) [offset = 154h] 1492 SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 60 ............... 28-42. SPI Pin Control Register 5 (SPIPC5) [offset = 28h] 1551 ............... 28-43. SPI Pin Control Register 6 (SPIPC6) [offset = 2Ch] 1552 List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 61 28-88. Multi-buffer RAM Transmit Data Register (TXRAM) [offset = Base + 000-1FFh] 1607 ....... 28-89. Multi-buffer RAM Receive Buffer Register (RXRAM) [offset = RAM Base + 200-3FFh] 1610 SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 62 29-33. SCI Set Interrupt Level Register (SCISETINTLVL) (offset = 14h) 1681 .......... 29-34. SCI Clear Interrupt Level Register (SCICLEARINTLVL) (offset = 18h) 1684 ................ 29-35. SCI Flags Register (SCIFLR) (offset = 1Ch) 1687 List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 63 30-23. SCI Pin I/O Control Register 1 (SCIPIO1) [offset = 40h] 1754 ............30-24. SCI Pin I/O Control Register 2 (SCIPIO2) [offset = 44h] 1755 SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 64 31-39. I2C Pins Slew Rate Select Register (I2CSRS) [offset = 6Ch] 1801 ........31-40. Difference between Normal Operation and Backward Compatibility Mode 1802 ..................32-1. EMAC and MDIO Block Diagram 1805 List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 65 ......32-49. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) (offset = 84h) 1887 ........32-50. Transmit Interrupt Mask Set Register (TXINTMASKSET) (offset = 88h) 1888 SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 66 .................. 33-6. Counter and Synchronization Block 1933 ..................... 33-7. Interrupts in eCAP Module 1934 ..............33-8. PWM Waveform Details of APWM Mode Operation 1935 List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 67 34-30. eQEP Watchdog Period Register (QWDPRD) [offset = 24h] 1982 ............34-31. eQEP Watchdog Timer Register (QWDTMR) [offset = 26h] 1982 ..............34-32. eQEP Control Register (QEPCTL) [offset = 28h] 1983 SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 68 2031 .................... 35-30. PWM-Chopper Submodule 2033 ..............35-31. PWM-Chopper Submodule Operational Details 2034 ....... 35-32. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only 2034 List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 69 35-78. Trip Zone Digital Compare Event Select Register (TZDCSEL) [offset = 24h] 2085 ..............35-79. Trip-Zone Select Register (TZSEL) [offset = 26h] 2086 ............35-80. Trip-Zone Enable Interrupt Register (TZEINT) [offset = 28h] 2088 SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 70 36-27. DMM Pin Control 5 (DMMPC5) [offset = 80h] 2148 ............... 36-28. DMM Pin Control 6 (DMMPC6) [offset = 84h] 2149 ............... 36-29. DMM Pin Control 7 (DMMPC7) [offset = 88h] 2151 List of Figures SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 71 ............38-5. EFC Self Test Cycles Register (EFCSTCY) [offset = 48h] 2194 ............38-6. EFC Self Test Cycles Register (EFCSTSIG) [offset = 4Ch] 2195 SPNU563A – March 2018 List of Figures Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 72 2-45. PLL Control Register 2 (PLLCTL2) Field Descriptions ............2-46. SYS Pin Control Register 10 (SYSPC10) Field Descriptions ..........2-47. Die Identification Register, Lower Word (DIEIDL) Field Descriptions List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 73 2-94. Peripheral Protection Clear Register 0 (PPROTCLR0) Field Descriptions ........2-95. Peripheral Protection Clear Register 1 (PPROTCLR1) Field Descriptions ........2-96. Peripheral Protection Clear Register 2 (PPROTCLR2) Field Descriptions SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 74 Error Generic Parity Register (ERR_GENERIC_PARITY) Field Descriptions ....4-9. Error Unexpected Transaction Register (ERR_UNEXPECTED_TRANS) Field Descriptions ..........4-10. Error Transaction ID Register (ERR_TRANS_ID) Field Descriptions List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 75 ............... 6-24. Pin Multiplexing Control Registers Field Descriptions ............... 6-25. Pin Multiplexing Control Registers Field Descriptions ............... 6-26. Pin Multiplexing Control Registers Field Descriptions SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 76 7-46. FSM Sector Register 2 (FSM_SECTOR2) Field Descriptions ..........7-47. Flash Bank Configuration Register (FCFG_BANK) Field Descriptions ....................7-48. POM Control Registers ..........7-49. POM Global Control Register (POMGLBCTRL) Field Descriptions List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 77 10-13. STC Current Interval Count Register (STCCICR) Field Descriptions ..........10-14. Self-Test Global Status Register (STCGSTAT) Field Descriptions ............ 10-15. Self-Test Fail Status Register (STCFSTAT) Field Descriptions SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 78 13-13. CCM-R5F Key Register 2 (CCMKEYR2) Field Descriptions ........13-14. CCM-R5F Polarity Control Register (CCMPOLCNTRL) Field Descriptions ............13-15. CCM-R5F Status Register 4 (CCMSR4) Field Descriptions List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 79 ......16-26. ESM Influence ERROR Pin Set/Status Register 7 (ESMIEPSR7) Field Descriptions ......16-27. ESM Influence ERROR Pin Clear/Status Register 7 (ESMIEPCR7) Field Descriptions SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 80 18-1. CRC Modes in Which DMA Request and Counter Logic are Active or Inactive ..............18-2. Modes in Which Interrupt Condition Can Occur ....................18-3. Interrupt Offset Mapping List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 81 19-12. IRQ Index Offset Vector Register (IRQINDEX) Field Descriptions ..........19-13. FIQ Index Offset Vector Register (FIQINDEX) Field Descriptions ..........19-14. FIQ/IRQ Program Control Registers (FIRQPR) Field Descriptions SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 82 20-37. FTC Interrupt Enable Set Register (FTCINTENAS) Field Descriptions ........... 20-38. FTC Interrupt Enable Reset (FTCINTENAR) Field Descriptions ..........20-39. LFS Interrupt Enable Set Register (LFSINTENAS) Field Descriptions List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 83 20-87. DMA Memory Protection Region 6 Start Address Register (DMAMPR6S) Field Descriptions ....20-88. DMA Memory Protection Region 6 End Address Register (DMAMPR6E) Field Descriptions SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 84 21-27. SDRAM Configuration Register (SDCR) Field Descriptions ........... 21-28. SDRAM Refresh Control Register (SDRCR) Field Descriptions ........... 21-29. Asynchronous n Configuration Register (CEnCFG) Field Descriptions List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 85 22-33. ADC Group2 Sampling Time Configuration Register (ADG2SAMP) Field Descriptions ..........22-34. ADC Event Group Status Register (ADEVSR) Field Descriptions ............22-35. ADC Group1 Status Register (ADG1SR) Field Descriptions SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 86 22-81. ADC Group1 Maximum Count Register (ADG1MAXCOUNT) Field Descriptions ........ 22-82. ADC Group2 Current Count Register (ADG2CURRCOUNT) Field Descriptions ........ 22-83. ADC Group2 Maximum Count Register (ADG2MAXCOUNT) Field Descriptions List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 87 23-47. Suppression Filter Enable Register (HETSFENA) Field Descriptions 1040 ..........23-48. Loop Back Pair Select Register (HETLBPSEL) Field Descriptions 1041 ..........23-49. Loop Back Pair Direction Register (HETLBPDIR) Field Descriptions 1042 SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 88 ................... 23-96. Event Encoding Format for WCAP 1128 ................. 23-97. Event Encoding Format for WCAPE 1130 ..................24-1. CPENA / TMBx Priority Rules 1139 List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 89 24-49. Current Frame Count Register (HTU CFCOUNT) Field Descriptions 1180 ....... 24-50. Application Examples for Setting the Transfer Modes of CP A and B of a DCP 1181 SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 90 26-25. Transfer Base Address (TBA) Field Descriptions 1285 ............26-26. Next Transfer Base Address (NTBA) Field Descriptions 1285 ............. 26-27. Base Address of Mirrored Status (BAMS) Field Descriptions 1286 List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 91 26-75. Transfer to System Memory Interrupt Enable Reset 3 (TSMIER3) Field Descriptions 1317 ......26-76. Transfer to System Memory Interrupt Enable Set 4 (TSMIES4) Field Descriptions 1318 SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 92 26-123. GTU Configuration Register 10 (GTUC10) Field Descriptions 1373 ........... 26-124. GTU Configuration Register 11 (GTUC11) Field Descriptions 1374 ........ 26-125. Communication Controller Status Vector Register (CCSV) Field Descriptions 1375 List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 93 27-7. CAN Control Register (DCAN CTL) Field Descriptions 1456 ............27-8. Error and Status Register (DCAN ES) Field Descriptions 1459 ............27-9. Error Counter Register (DCAN ERRC) Field Descriptions 1461 SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 94 28-21. SPI Pin Control Register 7 (SPIPC7) Field Descriptions 1554 ............28-22. SPI Pin Control Register 8 (SPIPC8) Field Descriptions 1555 ............. 28-23. SPI Transmit Data Register 0 (SPIDAT0) Field Descriptions 1556 List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 95 29-5. Response Length Info Using IDBYTE Field Bits [5:4] for LIN Standards Earlier than 1.3 1644 ............29-6. Response Length with SCIFORMAT[18:16] Programming 1644 SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 96 30-5. SCI Global Control Register 1 (SCIGCR1) Field Descriptions 1735 ............30-6. SCI Set Interrupt Register (SCISETINT) Field Descriptions 1738 ..........30-7. SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions 1740 List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 97 31-21. I2C Extended Mode Register (I2CEMDR) Field Descriptions 1794 ..............31-22. I2C Prescale Register (I2CPSC) Field Descriptions 1794 ............31-23. I2C Peripheral ID Register 1 (I2CPID1) Field Descriptions 1795 SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 98 32-34. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field ......................Descriptions 1875 ..........32-35. MDIO User Access Register 0 (USERACCESS0) Field Descriptions 1876 List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 99 32-81. Transmit Pause Timer Register (TXPAUSE) Field Descriptions 1913 .......... 32-82. MAC Address Low Bytes Register (MACADDRLO) Field Descriptions 1914 .......... 32-83. MAC Address High Bytes Register (MACADDRHI) Field Descriptions 1915 SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 100 35-1. ePWM Module Control and Status Register Set Grouped by Submodule 1999 ................35-2. Submodule Configuration Parameters 2000 ..................35-3. Time-Base Submodule Registers 2002 ....................35-4. Key Time-Base Signals 2003 List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 101 35-51. Digital Compare A Control Register (DCACTL) Field Descriptions 2101 ............ 35-52. Digital Compare Trip Select (DCTRIPSEL) Field Descriptions 2102 ........... 35-53. Digital Compare Filter Control Register (DCFCTL) Field Descriptions 2103 SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 102 37-10. Pins Used for Data Communication 2166 ............ 37-11. RTP Trace Enable Register (RTPTRENA) Field Descriptions 2167 ............37-12. RTP Global Status Register (RTPGSR) Field Descriptions 2169 List of Tables SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 103 38-5. EFC Error Status Register (EFCERRSTAT) Field Descriptions 2194 ..........38-6. EFC Self Test Cycles Register (EFCSTCY) Field Descriptions 2194 ..........38-7. EFC Self Test Cycles Register (EFCSTSIG) Field Descriptions 2195 SPNU563A – March 2018 List of Tables Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 104: Preface
SPNU597— TMS570LC43x Hercules™ Development Kit (HDK) User's Guide. Describes the board level operations of the TMS570LC43 Hercules Development Kit (HDK). The HDK is based on the Texas Instruments TMS570LC4357 Microcontroller. The TMS570LC43 HDK is a table top card that allows engineers and software developers to evaluate certain characteristics of the TMS570LC4357 microcontroller to determine if the microcontroller meets the designer’s application requirements as...
Page 105 TI Embedded Processors Wiki— Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. Trademarks Hercules, E2E are trademarks of Texas Instruments.
Page 106: Introduction
Chapter 1 SPNU563A – March 2018 Introduction ........................... Topic Page ............... Designed for Safety Applications .................... Family Description ................. Endianism Considerations Introduction SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 107: Designed For Safety Applications
A DMA driven hardware engine for the background calculation of CRC signatures during data transfers. • A centralized error reporting function including a status output pin to enable external monitoring of the device status. SPNU563A – March 2018 Introduction Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 108: Family Description
ECLK1 and ECLK2 terminals. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low frequency output can be monitored externally as an indicator of the device operating frequency. Introduction SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 109 With integrated safety features and a wide choice of communication and control peripherals, the TMS570LC43x is an ideal solution for high performance real time control applications with safety critical requirements. SPNU563A – March 2018 Introduction Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 110 N2HET2 SCI1 LIN1_TX LIN2/ LIN2_RX LIN2_TX SCI2 SCI3_RX SCI 3 SCI3_TX SCI4_RX SCI4 SCI4_TX I2C1_SDA I2C1 I2C1_SCL I2C2_SDA I2C2 I2C2_SCL Copyright © 2016, Texas Instruments Incorporated Introduction SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 111: Endianism Considerations
/**lt; 0xF448: CS to Transmit char T2CDELAY /**lt; 0xF449: Transmit to CS char T2EDELAY /**lt; 0xF44A: Transmit to ENA char C2EDELAY /**lt; 0xF44B: CS to ENA SPNU563A – March 2018 Introduction Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 112: Architecture
........................... Topic Page ..................... Introduction ..................Memory Organization ....................... Exceptions ......................Clocks ............System and Peripheral Control Registers Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 113: Introduction
Introduction www.ti.com Introduction The TMS570LC43x family of microcontrollers is based on the Texas Instruments TMS570 Architecture. This chapter describes specific aspects of the architecture as applicable to the TMS570LC43x family of microcontrollers. 2.1.1 Architecture Block Diagram The TMS570LC43x microcontrollers are based on the TMS570 Platform architecture, which defines the interconnect between the bus masters and the bus slaves.
Page 114 I2C2 DCAN4 w/ ECC eCAP STC1 FlexRay MibSPI1 1..6 CCM- ePWM MibSPI2 DCC2 1..7 MibSPI3 N2HET1 STC2 MibSPI4 N2HET2 MibSPI5 MibADC 1 LIN1/SCI1 MibADC 2 LIN2/SCI2 Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 115: Definitions Of Terms
These fuses are programmed during the initial factory test of the device. The eFuse controller is designed so that the state of the eFuses cannot be changed once the device is packaged. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 116 General-purpose Input/Output The GIO module allows up to 16 terminals to be used as general-purpose Input or Output. Each of these are also capable of generating an interrupt to the CPU. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 117 Idle and Off modes in this device behave the same from power consumption perspective. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 118: Bus Master / Slave Access Privileges
There is a checker for each master and slave attached to the CPU Interconnect Subsystem. The checker checks the expected behavior against the generated Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 119: Interconnect Subsystem Runtime Status
4-1. Also see Section 2.5.3 for details on the registers definition. Figure 2-2. PCR MasterID Filtering MasterID Address/Control ID Decode Addr Decode Peripheral Select N PCRx SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 120: Memory Organization
NOTE: After the swap with the flash memory-mapped to 0x08000000, only 512kB of the flash memory from 0x08000000 to 0x0807FFFF will be accessible by the bus masters. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 121 0x68000000 Async RAM 0x64000000 0x60000000 RESERVED 0x33FFFFFF R5F-0 Cache 0x30000000 RESERVED 0x0847FFFF RAM - ECC 0x08400000 RESERVED 0x0807FFFF RAM (512kB) 0x08000000 RESERVED 0x003FFFFF Flash (4MB) 0x00000000 SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 122: Memory-Map Table
TI OTP, Bank1 0xF008_2000 0xF008_3FFF Abort TI OTP, EEPROM 0xF008_E000 0xF008_FFFF Abort Bank TI OTP-ECC, Bank0 0xF00C_0000 0xF00C_03FF 512B Abort TI OTP-ECC, Bank1 0xF00C_0400 0xF00C_07FF 512B Abort Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 123 0xFB00_0000 0xFBFF_FFFF 16MB 512kB Accesses above 0xFB000200 generate abort. Memories under User PCR3 (Peripheral Segment 3) MIBSPI5 RAM PCS[5] 0xFF0A_0000 0xFF0B_FFFF 128kB Abort for accesses above SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 124 0x2000 and ends at address offset 0x217F. Wrap around for accesses between offsets 0x0180 and 0x3FFF. Abort generation for accesses beyond offset 0x4000. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 125 CoreSight TPIU CSCS[3] 0xFFA0_3000 0xFFA0_3FFF Reads return zeros, writes have no effect CSCS[4] 0xFFA0_4000 0xFFA0_4FFF Reads return zeros, writes have no effect SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 126 DCAN1 PS[8] 0xFFF7_DC00 0xFFF7_DDFF 512B 512B Reads return zeros, writes have no effect DCAN2 PS[8] 0xFFF7_DE00 0xFFF7_DFFF 512B 512B Reads return zeros, writes have no effect Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 127 TI during have no effect test STC2 (NHET1/2) PPSE[2] 0xFFFF_0800 0xFFFF_08FF 256B 256B Reads return zeros, writes have no effect PPSE[2] 0xFFFF_0A00 0xFFFF_0AFF 256B 256B Abort SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 128 System Module - PPS[7] 0xFFFF_FF00 0xFFFF_FFFF 256B 256B Reads return Frame 1 (see platform zeros, writes architecture have no effect specification) Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 129: Flash On Microcontrollers
The Flash banks are 288-bit wide bank with ECC support. • The flash bank7 can be programmed while executing code from flash bank0. • Code execution is not allowed from flash bank7. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 130 0x0038_0000 0x0039_FFFF 128K Bytes 0x003A_0000 0x003B_FFFF 128K Bytes 0x003C_0000 0x003D_FFFF 128K Bytes 0x003E_0000 0x003F_FFFF Bank 7: 128 kBytes 4K Bytes 0xF020_0000 0xF020_0FFF 4K Bytes 0xF021_F000 0xF021_FFFF Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 131 Table 2-4 shows only those registers that associate the bits to a specific interface for this device. See EPC chapter for the full list of registers. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 132 CPU SCR Uncorrectable ECC for DMA I/F Err Gen UERR Addr Reg Err Stat CPU SCR Uncorrectable ECC for PS_SCR_M I/F Uncorrectable Error Capture Block Unorrectable Error Event Source EPC Module Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 133 • Uncorrectable error address register for the UERRADDR0 31:0 DMA interface DMA interface Uncorrectable ECC for • Uncorrectable error address register for the UERRADDR1 31:0 PS_SCR_M interface PS_SCR_M interface SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 134: On-Chip Sram
HTU2 1 to 6 Two-port MIBSPI4 1 to 4 Two-port MIBSPI5 1 to 4 Two-port N2HET2 1 to 12 Two-port Two-port FRAY_INBUF_OUTBUF 1 to 8 Two-port Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 135 Single-port Single-port Single-port Reserved Single-port Single-port Single-port Single-port Reserved Single-port Single-port Single-port Single-port Single-port Single-port FRAY_TRBUF_MSGRAM 9 to 11 Single-port CPGMAC_CPPI Single-port R5_DCACHE_Dirty Single-port Reserved Single-port SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 136 NOTE: PBIST ROM_CLK can be prescaled from GCLK1 via ROM_DIV bits of the MSTGCR register. The valid ratio is either /1, /2 or /4 or /8. See Section 2.5.1.20 for detail. Maximum PBIST ROM_CLK frequency supported is 82.5MHz. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 137 DEV_MMIDONEn (where n = 31:0) (from memory modules to System module) Black indicates System register activity. Gray indicates inter-module activity, not accessible via System register. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 138 This is independent of whether the application has already initialized these RAMs using the auto-initialization method or not. The MibSPIx modules need to be released from reset by writing 1 to their SPIGCR0 registers before starting auto-initialization on their respective RAMs. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 139: Exceptions
An error occurring on an instruction fetch generates a prefetch abort. Errors occurring on data accesses generate data aborts. Aborts are also categorized as being either precise or imprecise. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 140 The A-bit in the CPSR is set by default. This means that no imprecise abort exception will occur. The application must enable imprecise abort exception generation by clearing the A- bit of the CPSR. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 141: System Software Interrupts
SSI registers. Both CPUs will see the SSI registers at the same address. The system module decodes the unique master ID corresponding to the CPU's access to the banked registers. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 142: Clocks
“Oscillator and PLL” user guide for more information on enabling / disabling the oscillator and PLL. On the TMS570LC43x microcontrollers, the clock sources 0, 4, and 5 are enabled by default. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 143: Clock Domains
VCLKA4_DIVR VCLKACON1.20 VCLK VCLKACON1[19:16] • Default frequency is VCLKA4/2 • Is disabled separately via the VCLKACON1 register's VCLKA4_DIV_CDDIS bit, if the VCLKA4 is not already disabled SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 144 VCLK frequency divided by 3. The application can configure the RTI1DIV field of the RCLKSRC register for dividing the selected clock source frequency by 1, 2, 4 or 8 to meet this requirement. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 145: Low Power Modes
Flash pump sleep -> active transition time Sleep None None CAN message, HF LPO SCI message Flash bank sleep -> standby transition time Flash bank standby -> active transition time SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 146: Clock Test Mode
The clock test mode is controlled by the CLKTEST register in the system module register frame (see Section 2.5.1.31). The clock test mode is enabled by writing 0x5 to the CLK_TEST_EN field. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 147 Flash HD Pump Oscillator 1111 Oscillator Valid Status 10000 Reserved 10001 HCLK 10010 VCLK 10011 VCLK2 10100 VCLK3 10101-10110 Reserved 10111 EMAC clock output 11000-11111 Reserved SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 148: Embedded Trace Macrocell (Etm-R5)
The TMS570LC43x microcontrollers are targeted for use in several safety-critical applications. The following sections describe the internal or external monitoring mechanisms that detect and signal clock source failures. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 149 Section 2.4.6.4.1 Section 2.4.6.4.2. This mechanism can be used to use a known-good clock to measure the frequency of another clock. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 150 Table 2-17. DCC2 Counter 1 Clock / Signal Inputs Key [3–0] Clock Source [3–0] Clock / Signal Name Reserved PLL2 post_ODCLK/8 PLL2 post_ODCLK/16 3h-7h Reserved 8h-Fh VCLK All other values any value N2HET2[0] Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 151: System And Peripheral Control Registers
System Software Interrupt Request 1 Register Section 2.5.1.35 SSIR2 System Software Interrupt Request 2 Register Section 2.5.1.36 SSIR3 System Software Interrupt Request 3 Register Section 2.5.1.37 SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 152 Global Status Register Section 2.5.1.48 DEVID Device Identification Register Section 2.5.1.49 SSIVEC Software Interrupt Vector Register Section 2.5.1.50 SSIF System Software Interrupt Flag Register Section 2.5.1.51 Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 153 The ECLK pin is an output. Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the SYSPC1 register. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 154 Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the SYSPC1 register. The ECLK pin is placed in output mode by setting the ECPCLKDIR bit to 1 in the SYSPC2 register. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 155 Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the SYSPC1 register. The ECLK pin is placed in output mode by setting the ECPCLKDIR bit to 1 in the SYSPC2 register. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 156 Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the SYSPC1 register. The ECLK pin is placed in input mode by clearing the ECPCLKDIR bit to 0 in the SYSPC2 register. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 157 Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the SYSPC1 register. The ECLK pin is placed in input mode by clearing the ECPCLKDIR bit to 0 in the SYSPC2 register. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 158 Clock Source 5 High frequency LPO (Low Power Oscillator) clock Clock Source 6 PLL2 Clock Source 7 EXTCLKIN2 NOTE: Non-implemented clock sources should not be enabled or used. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 159 CSDIS register (offset 30h), the CSDISSET register (offset 34h), and the CSDISCLR register (offset 38h). NOTE: A list of the available clock sources is shown in the Table 2-29. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 160 CSDIS register (offset 30h), the CSDISSET register (offset 34h) and the CSDISCLR register (offset 38h). NOTE: A list of the available clock sources is shown in the Table 2-29. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 161 VCLK2 domain off. The VCLK2 domain is enabled. The VCLK2 domain is disabled. VCLKPOFF VCLK_periph domain off. The VCLK_periph domain is enabled. The VCLK_periph domain is disabled. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 162 The HCLK and VCLK_sys domains are enabled. The HCLK and VCLK_sys domains are disabled. GCLK1OFF GCLK1 domain off. The GCLK1 domain is enabled. The GCLK1 domain is disabled. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 163 Read: The VCLK2 domain is enabled. Write: The VCLK2 domain is unchanged. Read: The VCLK2 domain is disabled. Write: The VCLK2 domain is set to the enabled state. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 164 Read: The GCLK1 domain is enabled. Write: The GCLK1 domain is unchanged. Read: The GCLK1 domain is disabled. Write: The GCLK1 domain is set to the enabled state. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 165 Read: The VCLK2 domain is enabled. Write: The VCLK2 domain is unchanged. Read: The VCLK2 domain is disabled. Write: The VCLK2 domain is cleared to the enabled state. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 166 Read: The GCLK1 domain is enabled. Write: The GCLK1 domain is unchanged. Read: The GCLK1 domain is disabled. Write: The GCLK1 domain is cleared to the enabled state. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 167 Clock source5 is the source for GCLK1, HCLK, VCLK, VCLK2. Clock source6 is the source for GCLK1, HCLK, VCLK, VCLK2. Clock source7 is the source for GCLK1, HCLK, VCLK, VCLK2. 8h-Fh Reserved SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 168 VCLK is the source for peripheral asynchronous clock1. NOTE: Non-implemented clock sources should not be enabled or used. A list of the available clock sources is shown in Table 2-29. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 169 Clock source7 is the source for RTICLK1. 8h-Fh VCLK is the source for RTICLK1. NOTE: A list of the available clock sources is shown in the Table 2-29. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 170 Note: If the valid bit of the source of a clock domain is not set (that is, the clock source is not fully stable), the respective clock domain is disabled. NOTE: A list of the available clock sources is shown in the Table 2-29. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 171 Note: It is recommended that a value of Ah be used to disable the memory self-test controller. This value will give maximum protection from a bit flip inducing event that would inadvertently enable the controller. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 172 Note: It is recommended that a value of 5h be used to disable memory hardware initialization. This value will give maximum protection from an event that would inadvertently enable the controller. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 173 Note: Software should ensure that both the memory self-test global enable key (MSTGENA) and the memory hardware initialization global key (MINITGENA) are not enabled at the same time. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 174 Read: Memory self-test is not completed. Write: A write of 0 has no effect. Read: Memory self-test is completed. Write: The bit is cleared to 0. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 175 Reserved REFCLKDIV R/WP-0 R/WP-3h PLLMUL R/WP-4100h LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 176 100h VCO CLK INT CLK 5B00h x 92 VCO CLK INT CLK 5C00h x 93 VCO CLK INT CLK FF00h x 256 VCO CLK INT CLK Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 177 If frequency modulation is disabled and SPR_AMOUNT is changed, there is no effect on the PLL output clock. NV = 1/2048 NV = 2/2048 1FFh NV = 512/2048 SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 178 ECPCLK slew control. This bit controls between the fast or slow slew mode. Fast mode is enabled; the normal output buffer is used for this pin. Slow mode is enabled; slew rate control is used for this pin. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 179 NOTE: Die Identification Information The die identification information will vary from unit to unit. This information is programmed by TI as part of the initial device test procedure. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 180 Read: OSC freq is > 20MHz and ≤ 80MHz. Write: A write of 1 has no effect. 15-13 Reserved Reads return 0. Writes have no effect. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 181 100.00% Default at Reset. 104.09 108.17 112.32 116.41 120.67 124.42 128.38 132.24 136.15 140.15 143.94 148.02 151.80x 155.50x 159.35% Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 182 65.78 70.75 75.63 80.61 85.39 90.23 95.11 100.00% Default at Reset 104.84 109.51 114.31 119.01 123.75 128.62 133.31 138.03 142.75 147.32 152.02 156.63 161.38 165.90 170.42 Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 183 ECPCLKFUN bit to 1 in the SYSPC1 register. Clock going to ECLK pin is enabled. Others Clock going to ECLK pin is disabled. 15-12 Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 184 Flash HD Pump Oscillator Reserved HCLK VCLK VCLK2 VCLK3 15h-16h Reserved EMAC clock output 18h-1Fh Reserved NOTE: Non-implemented clock sources should not be enabled or used. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 185 Register key enable. ALL the bits can be written to only when the key is enabled. On reset, these bits will be set to 5h. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 186 Register key disable. All bits in this register will maintain their default value and cannot be (except Ah) written. Register key enable. ALL the bits can be written to only when the key is enabled. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 187 FBSLIP occurs when the KEY is programmed and a non-zero value is present in the COUNT field. 15-0 Reserved Reads return 0 or 1 and write in privilege mode. The functionality of this bit is unavailable in this device. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 188 SSKEY1 field matches the key (75h); therefore, byte writes cannot be performed on the SSDATA1 field. NOTE: This register is mirrored at offset FCh for compatibility reasons. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 189 SSKEY2 field matches the key (84h); therefore, byte writes cannot be performed on the SSDATA2 field. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 190 SSKEY3 field matches the key (93h); therefore, byte writes cannot be performed on the SSDATA3 field. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 191 SSKEY4 field matches the key (A2h); therefore, byte writes cannot be performed on the SSDATA4 field. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 192 Reads return 0. Writes have no effect. Reserved Reads return 0 or 1 depends on what is written in privileged mode. The functionality of this bit is unavailable in this device. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 193 Program memory (Flash) starts at address 0. eSRAM starts at address 800 0000h. Swapped memory-map: eSRAM starts at address 0. Program memory (Flash) starts at address 800 0000h. Others The device memory-map is unchanged. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 194 Reads return 0. Writes have no effect. CPU RESET CPU RESET. Only the CPU is reset whenever this bit is toggled. There is no system reset. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 195 Peripheral enable bit. The application must set this bit before accessing any peripheral. The global peripheral/peripheral memory frames are in reset. All peripheral/peripheral memory frames are out of reset. Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 196 VBUS clock or OSCIN as shown in the formula: V C L K o rO S C I E C L K E C P D IV Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 197 Software reset bits. Setting RESET1 or clearing RESET0 causes a system software reset. No reset will occur. 0, 2h-3h A global system reset will occur. 13-0 Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 198 No CPUx reset has occurred because of an interconnect self-test check. A reset has occurred to the CPUx because of the interconnect self-test check. Reserved Reads return 0. Writes have no effect. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 199 The external reset pin has not asserted a reset. A reset has been caused by the external reset pin. Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 200 JTAG data register. In either case, the autoload machine was not able or not allowed to complete its operation. Others Read: Reserved. Write: These bits are cleared to 0. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 201 Read: No oscillator failure has been detected. Write: The bit is unchanged. Read: An oscillator failure has been detected. Write: The bit is cleared to 0. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 202 0-1Fh Version. These bits provide the revision of the device. PLATFORM ID The device is part of the TMS570Px family. The TMS570Px ID is always 5h. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 203 A software interrupt has been generated by writing the correct key value to The SSIR3 register. A software interrupt has been generated by writing the correct key value to The SSIR4 register. 5h-FFh Reserved SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 204 Read: No IRQ/FIQ interrupt was generated since the bit was last cleared. Write: The bit is unchanged. Read: An IRQ/FIQ interrupt was generated. Write: The bit is cleared to 0. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 205: Secondary System Control Registers (Sys2)
Section 2.5.2.10 DIEIDH_REG1 Die Identification Register Upper Word Section 2.5.2.11 DIEIDL_REG2 Die Identification Register Lower Word Section 2.5.2.12 DIEIDH_REG3 Die Identification Register Upper Word Section 2.5.2.13 SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 206 User and privileged mode (read): Privileged mode (write): 100h VCOCLK2 INTCLK2 5B00h x 92 VCOCLK2 INTCLK2 5C00h x 93 VCOCLK2 INTCLK2 FF00h x 256 VCOCLK2 INTCLK2 Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 207 Reads return 0. Writes have no effect. 26-24 CLKDIV Clock divider/prescaler for CPU clock during logic BIST 23-0 Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 208 VBUS clock or OSCIN as shown in the formula: V C L K o rO S C I E C L K E C P D IV Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 209 Reserved Reads return 0. Writes have no effect. VCLK3R VBUS clock3 ratio. The ratio is HCLK divide by 1. The ratio is HCLK divided by 16. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 210 Reserved 109h Reserved NOTE: Non-implemented clock sources should not be enabled or used. A list of the available clock sources is shown in the Table 2-29. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 211 HCLK is equal to GCLK1 divide by 1. HCLK is equal to GCLK1 divide by 2. HCLK is equal to GCLK1 divide by 3. HCLK is equal to GCLK1 divide by 4. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 212 PLL RFSLIP filtering is enabled. Recommended to program Ah in this bit field. Enabling of the PLL RFSLIP occurs when the KEY is programmed and a non- zero value is present in the COUNT field. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 213 Disable ECC error generation for ECC errors detected on DMA Port A master by the CPU Interconnect Subsystem. Enable ECC error generation for ECC errors detected on DMA Port A master by the CPU Interconnect Subsystem. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 214 NOTE: Die Identification Information The die identification information will vary from unit to unit. This information is programmed by TI as part of the initial device test procedure. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 215 Value Description 31-0 DIEIDL2(95-64) 0-FFFF FFFFh This read-only register contains the lower word (95:64) of the die ID information. The contents of this register is reserved. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 216 Value Description 31-0 DIEIDH2(127-96) 0-FFFF FFFFh This read-only register contains the upper word (127:97) of the die ID information. The contents of this register is reserved. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 217: Peripheral Central Resource (Pcr) Control Registers
Peripheral Frame 0 Master-ID Protection Register_L Section 2.5.3.30 304h PS0MSTID_H Peripheral Frame 0 Master-ID Protection Register_H Section 2.5.3.31 308h PS1MSTID_L Peripheral Frame 1 Master-ID Protection Register_L Section 2.5.3.32 SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 218 Peripheral Frame 23 Master-ID Protection Register_H Section 2.5.3.32 3C0h PS24MSTID_L Peripheral Frame 24 Master-ID Protection Register_L Section 2.5.3.32 3C4h PS24MSTID_H Peripheral Frame 24 Master-ID Protection Register_H Section 2.5.3.32 Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 219 Section 2.5.3.38 Register_H 460h PPSE4MSTID_L Privilege Peripheral Extended Frame 4 Master-ID Protection Section 2.5.3.38 Register_L 464h PPSE4MSTID_H Privilege Peripheral Extended Frame 4 Master-ID Protection Section 2.5.3.38 Register_H SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 220 Section 2.5.3.38 Register_H 4D0h PPSE18MSTID_L Privilege Peripheral Extended Frame 18 Master-ID Protection Section 2.5.3.38 Register_L 4D4h PPSE18MSTID_H Privilege Peripheral Extended Frame 18 Master-ID Protection Section 2.5.3.38 Register_H Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 221 Peripheral Memory Frame Master-ID Protection Register1 Section 2.5.3.39 548h PCS2MSTID Peripheral Memory Frame Master-ID Protection Register2 Section 2.5.3.39 54Ch PCS3MSTID Peripheral Memory Frame Master-ID Protection Register3 Section 2.5.3.39 SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 222 Privileged Peripheral Memory Frame Master-ID Protection Section 2.5.3.40 Register5 5D8h PPCS6MSTID Privileged Peripheral Memory Frame Master-ID Protection Section 2.5.3.40 Register6 5DCh PPCS7MSTID Privileged Peripheral Memory Frame Master-ID Protection Section 2.5.3.40 Register7 Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 223 Read: The peripheral memory framen can be written to only in privileged mode, but it can be read in both user and privileged modes. Write: The corresponding bit in PMPROTSET1 and PMPROTCLR1 registers is set to 1. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 224 Read: The peripheral memory framen can be written to only in privileged mode, but it can be read in both user and privileged modes. Write: The corresponding bit in PMPROTSET1 and PMPROTCLR1 registers is cleared to 0. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 225 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be read in both user and privileged modes. Write: The corresponding bit in PPROTSET0 and PPROTCLR0 registers is set to 1. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 226 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be read in both user and privileged modes. Write: The corresponding bit in PPROTSET2 and PPROTCLR2 registers is set to 1. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 227 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be read in both user and privileged modes. Write: The corresponding bit in PPROTSET0 and PPROTCLR0 registers is cleared to 0. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 228 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be read in both user and privileged modes. Write: The corresponding bit in PPROTSET2 and PPROTCLR2 registers is cleared to 0. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 229 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be read in both user and privileged modes. Write: The corresponding bit in PPROTSET3 and PPROTCLR3 registers is cleared to 0. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 230 Write: The bit is unchanged. Read: The peripheral memory clock[63-32] is inactive. Write: The corresponding bit in the PCSPWRDWNSET1 and PCSPWRDWNCLR1 registers is set to 1. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 231 Write: The bit is unchanged. Read: The peripheral memory clock[63-32] is inactive. Write: The corresponding bit in the PCSPWRDWNSET1 and PCSPWRDWNCLR1 registers is cleared to 0. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 232 Write: The bit is unchanged. Read: The clock to the peripheral select quadrant is inactive. Write: The corresponding bit in PSPWRDWNSET0 and PSPWRDWNCLR0 registers is set to 1. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 233 Write: The bit is unchanged. Read: The clock to the peripheral select quadrant is inactive. Write: The corresponding bit in PSPWRDWNSET2 and PSPWRDWNCLR2 registers is set to 1. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 234 Write: The bit is unchanged. Read: The clock to the peripheral select quadrant is inactive. Write: The corresponding bit in PSPWRDWNSET0 and PSPWRDWNCLR0 registers is cleared to 0. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 235 Write: The bit is unchanged. Read: The clock to the peripheral select quadrant is inactive. Write: The corresponding bit in PSPWRDWNSET2 and PSPWRDWNCLR2 registers is cleared to 0. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 236 Read: The clock to the debug frame is active. Write: The bit is unchanged. Read: The clock to the debug frame is inactive. Write: Set the bit to 1. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 237 Read: All master-ID registers are unlocked and available for writes. Write: Writes to master-ID registers are unlocked. Others Read: Writes to all master-ID registers are locked. Write: Write to master-ID registers are locked. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 238 1010 to enable Master-ID Check functionality. Read: The master-ID check is enabled. Write: Enable master-ID check. Others Read: The master-ID check is disabled. Write: Disable master-ID check. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 239 1010 to enable Diagnostic Mode. Read: The diagnostic mode is enabled. Write: Enable diagnostic mode. Others Read: The diagnostic mode is disabled. Write: Disable diagnostic mode. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 240 Read: The corresponding master-ID is permitted to access the peripheral mapped to this quadrant. Write: Enable the permission of the corresponding master to access the peripheral mapped to this quadrant. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 241 Read: The corresponding master-ID is permitted to access the peripheral mapped to this quadrant. Write: Enable the permission of the corresponding master to access the peripheral mapped to this quadrant. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 242 Write: Disable the permission of the corresponding master to access the peripheral. Read: The corresponding master-ID is permitted to access the peripheral. Write: Enable the permission of the corresponding master to access the peripheral. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 243 Write: Disable the permission of the corresponding master to access the peripheral. Read: The corresponding master-ID is permitted to access the peripheral. Write: Enable the permission of the corresponding master to access the peripheral. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 244 Read: The corresponding master-ID is permitted to access the peripheral mapped to this quadrant. Write: Enable the permission of the corresponding master to access the peripheral mapped to this quadrant. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 245 Write: Disable the permission of the corresponding master to access the peripheral. Read: The corresponding master-ID is permitted to access the peripheral. Write: Enable the permission of the corresponding master to access the peripheral. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 246 Write: Disable the permission of the corresponding master to access the peripheral. Read: The corresponding master-ID is permitted to access the peripheral. Write: Enable the permission of the corresponding master to access the peripheral. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 247 Read: The corresponding master-ID is permitted to access the peripheral mapped to this quadrant. Write: Enable the permission of the corresponding master to access the peripheral mapped to this quadrant. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 248 Write: Disable the permission of the corresponding master to access the peripheral. Read: The corresponding master-ID is permitted to access the peripheral. Write: Enable the permission of the corresponding master to access the peripheral. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 249 Write: Disable the permission of the corresponding master to access the peripheral. Read: The corresponding master-ID is permitted to access the peripheral. Write: Enable the permission of the corresponding master to access the peripheral. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 250 Write: Disable the permission of the corresponding master to access the peripheral. Read: The corresponding master-ID is permitted to access the peripheral. Write: Enable the permission of the corresponding master to access the peripheral. Architecture SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 251 Write: Disable the permission of the corresponding master to access the peripheral. Read: The corresponding master-ID is permitted to access the peripheral. Write: Enable the permission of the corresponding master to access the peripheral. SPNU563A – March 2018 Architecture Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 252: Scr Control Module (Scm)
This chapter describes the SCR control module (SCM). SCR is the CPU Interconnect Subsystem..........................Topic Page ......................Overview ..................... Module Operation ....................How to Use SCM ....................SCM Registers SCR Control Module (SCM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 253: Overview
• Provides the ability to override parity polarity of the interconnect hardware checker so that the parity detection logic can be self-tested. SPNU563A – March 2018 SCR Control Module (SCM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 254: System Block Diagram
Sdc_test_finished Dtc_soft_reset (3:0) active_ia_o(n-1:0) IA_n TA_m active_ta_o(m-1:0) n is the maximum number of IA. m is the maximum number of TA. SCR Control Module (SCM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 255: Module Operation
Any of these status bits can be cleared by a privilege write to the individual bit. The write clear from CPU to these status bits will always take higher priority than setting of the status bits from the interconnect. SPNU563A – March 2018 SCR Control Module (SCM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 256: Scm Control Block
MMR Key To_clear decode Dtc_soft_reset (3:0) Dtc_soft_reset MMR Key Hwchkr_sdc_soft_reset logic decode Global_error_clr MMR Key Global_error_clr decode PAR DIAG EN MMR Key Parity_diagnostic_enable decode SCR Control Module (SCM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 257: How To Use Scm
Note that the hardware only does parity inversion check in one cycle so that it does not block out CPU access to Flash and RAM on subsequence cycle. SPNU563A – March 2018 SCR Control Module (SCM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 258: How To Initiate Self-Test Sequence
6. Once self-test completes, CPU will boot up from 0x0 again and you need to read interconnect diagnostic register to inspect for any error detected during self-test. Refer to device technical reference manual for base address. SCR Control Module (SCM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 259: How To Configure Timeout Check
The interconnect hardware checker real time counter needs to be reset to 0 in order to restart properly. SPNU563A – March 2018 SCR Control Module (SCM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 260: Scm Registers
A0Bh Indicates functionally equivalent module family. 15-11 RTL version number. 10-8 MAJOR Major revision number. CUSTOM Indicates device-specific implementation. MINOR Minor revision number. SCR Control Module (SCM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 261: Scm Control Register (Scmcntrl)
5h. Read: Sticky key. All other values Reserved Write in Privilege: Enable global error clear. All other values Reserved SPNU563A – March 2018 SCR Control Module (SCM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 262: Scm Compare Threshold Counter Register (Scmthreshold)
Reset values equals to the values of REQ2ACCEPT_RST generic parameter. Read: Values of counter. Write in Privilege: Values of counter. SCR Control Module (SCM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 263: Scm Initiator Error0 Status Register (Scmiaerr0Stat)
No request to response time out error happens on IAn. Request to response time out error happens on IAn. Write in Privilege: No effect. Clear this flag bit. SPNU563A – March 2018 SCR Control Module (SCM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 264: Scm Initiator Active Status Register (Scmiastat)
TAn.Refer to Interconnect chapter of the TRM for mapping of slave port to the SCMTASTAT register bit. No pending transaction in TAn. Pending transaction in TAn. SCR Control Module (SCM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 265: Interconnect
This chapter describes the two interconnects in the microcontroller..........................Topic Page ......................Overview ..............Peripheral Interconnect Subsystem ................CPU Interconnect Subsystem ..................SDC MMR Registers SPNU563A – March 2018 Interconnect Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 266: Overview
Masters PCRx Access Mode CRC1 CRC2 PCR1 PCR2 PCR3 PS_SCR_S Port User/Privilege Read/Write DMA Port B User HTU1 Privilege HTU2 Privilege User User Privilege EMAC User Interconnect SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 267: Accessing Pcrx And Crcx Slave
PS_SCR_S slave where it then becomes a master on the CPU Interconnect Subsystem as PS_SCR_M. The request appearing on the PS_SCR_M is then decoded and routed to the intended slave by the CPU Interconnect Subsystem. SPNU563A – March 2018 Interconnect Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 268: Cpu Interconnect Subsystem
All bus masters on the CPU Interconnect Subsystem have a point to point connection to the EMIF slave without going through ACP for coherency check. Coherency maintenance on the EMIF between the CPU and other masters will need to be handled by software. Interconnect SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 269: Ecc Generation And Evaluation
0xA key to the GLOBAL_ERROR_CLR bits of the SCMCNTRL register in the SCR Control Module (SCM). See the SCM Chapter for more information. SPNU563A – March 2018 Interconnect Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 270: Interconnect Self-Test
Application needs to write 0xA key to the TO_CLEAR bits of the SCMCNTRL register to reset the timeout logic inside the CPU Interconnect Subsystem as part of the error handling in the ISR. Interconnect SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 271: Interconnect Runtime Status
Bit 10 Bit 11 Bit 12 Bit 13 SCMTASTAT for the corresponding slave PCR1 PCR2 PCR3 CRC1 CRC2 SDC MMR to be processed by the interconnect SPNU563A – March 2018 Interconnect Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 272: Sdc Mmr Registers
Section 4.4.8 SERR_UNEXPECTED_MID Slave Error Unexpected Master ID register Section 4.4.9 SERR_ADDR_DECODE Slave Error Address Decode Register Section 4.4.10 SERR_USER_PARITY Slave Error User Parity Register Section 4.4.11 Interconnect SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 273: Sdc Status Register (Sdc_Status)
Positive test OK status for self-test. Positive test has failed. Positive test has passed. PT_RUN Positive test on-going status. Positive test has ended. Positive test is on-going. SPNU563A – March 2018 Interconnect Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 274: Sdc Control Register (Sdc_Control)
0: PS_SCR_M master bit 1: POM master bit 2: DMA PortA master bit 3: Reserved bit 4: Cortex-R5F CPU master. bit 5: ACP-M master Interconnect SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 275: Error Unexpected Transaction Register (Err_Unexpected_Trans)
0: PS_SCR_M master bit 1: POM master bit 2: DMA PortA master bit 3: Reserved bit 4: Cortex-R5F CPU master. bit 5: ACP-M master SPNU563A – March 2018 Interconnect Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 276: Error Transaction Signature Register (Err_Trans_Signature)
0: PS_SCR_M master bit 1: POM master bit 2: DMA PortA master bit 3: Reserved bit 4: Cortex-R5F CPU master. bit 5: ACP-M master Interconnect SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 277: Error User Parity Register (Err_User_Parity)
1: L2 Flash PortB slave bit 2: L2 Flash PortA slave bit 3: EMIF slave bit 4: Reserved bit 5: Cortex-R5F CPU AXI slave bit 6: ACP-S slave SPNU563A – March 2018 Interconnect Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 278: Slave Error Address Decode Register (Serr_Addr_Decode)
1: L2 Flash PortB slave bit 2: L2 Flash PortA slave bit 3: EMIF slave bit 4: Reserved bit 5: Cortex-R5F CPU AXI slave bit 6: ACP-S slave Interconnect SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 279: Power Management Module (Pmm)
Power Management Module (PMM) This chapter describes the power management module (PMM)..........................Topic Page ......................Overview ....................Power Domains ....................PMM Operation ....................PMM Registers SPNU563A – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 280: Overview
Overview The microcontroller is part of the family of microcontrollers from Texas Instruments for safety-critical applications. Several functions are implemented on this microcontroller targeted towards varied applications. The core logic is divided into several domains that can be independently turned on or off based on the application’s requirements.
Page 281 Overview www.ti.com Figure 5-1. PMM Block Diagram SPNU563A – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 282: Power Domains
RTP, DMM SRAM, Interconnect, Clock control, Basic HTU2, SCI3, SCI4, peripheral set) I2C1, I2C2 FlexRay, FTU Ethernet, EMIF ePWM[1..7], eCAP[1..6], eQEP[1..2] Switchable domains Power Management Module (PMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 283: Pmm Operation
2. Write 0xA to the LOGICPDPWRCTRL0 register to power down the domain. 3. Poll for LOGICPDPWRSTATx to become “00”. The power domain is now powered down. SPNU563A – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 284: Reset Management
The compare match test is terminated if a compare mismatch is detected. The compare match test takes 4 cycles to complete when the test passes. Power Management Module (PMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 285: Pmm Registers
LogicPD PSCON Diagnostic Compare Status Register 1 Section 5.4.14 LPDDCSTAT2 LogicPD PSCON Diagnostic Compare Status Register 2 Section 5.4.15 ISODIAGSTAT Isolation Diagnostic Status Register Section 5.4.16 SPNU563A – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 286: Logic Power Domain Control Register (Logicpdpwrctrl0)
Reserved Any other value Read: Power domain PD5 is in Active state. Write: Power domain PD5 is commanded to switch to Active state. Power Management Module (PMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 287: Logic Power Domain Control Register (Logicpdpwrctrl1)
Read: Power domain PD6 is in Active state. Write: Power domain PD6 is commanded to switch to Active state. 23-0 Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 288: Power Domain Clock Disable Register (Pdclkdisreg)
Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. Write in Privileged Mode only. Enable clocks to logic power domain PD2. Disable clocks to logic power domain PD2. Power Management Module (PMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 289: Power Domain Clock Disable Set Register (Pdclkdissetreg)
Read in User and Privileged Mode returns the current value of PDCLK_DISSET[0]. Write in Privileged Mode only. No effect to state of clocks to power domain PD2. Disable clocks to logic power domain PD2. SPNU563A – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 290: Power Domain Clock Disable Clear Register (Pdclkdisclrreg)
Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. Write in Privileged Mode only. No effect to state of clocks to power domain PD2. Enable clocks to logic power domain PD2. Power Management Module (PMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 291: Logic Power Domain Pd2 Power Status Register (Logicpdpwrstat0)
Logic power domain PD2 is switched OFF. Logic power domain PD2 is in Idle state. Reserved Logic power domain PD2 is in Active state. SPNU563A – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 292: Logic Power Domain Pd3 Power Status Register (Logicpdpwrstat1)
Logic power domain PD3 is switched OFF. Logic power domain PD3 is in Idle state. Reserved Logic power domain PD3 is in Active state. Power Management Module (PMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 293: Logic Power Domain Pd4 Power Status Register (Logicpdpwrstat2)
Logic power domain PD4 is switched OFF. Logic power domain PD4 is in Idle state. Reserved Logic power domain PD4 is in Active state. SPNU563A – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 294: Logic Power Domain Pd5 Power Status Register (Logicpdpwrstat3)
Logic power domain PD5 is switched OFF. Logic power domain PD5 is in Idle state. Reserved Logic power domain PD5 is in Active state. Power Management Module (PMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 295: Logic Power Domain Pd6 Power Status Register (Logicpdpwrstat4)
Logic power domain PD6 is switched OFF. Logic power domain PD6 is in Idle state. Reserved Logic power domain PD6 is in Active state. SPNU563A – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 296: Global Control Register 1 (Globalctrl1)
Disable automatic clock wake up. The application must enable clocks by clearing the correct bit in the PDCLK_DIS register. Enable automatic clock wake up when a power domain transitions to Active state. Power Management Module (PMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 297: Global Status Register (Globalstat)
Read in User and Privileged mode returns the current value of MKEY. Write in Privileged mode only. Lock Step mode Self-test mode Error Forcing mode Self-test Error Forcing Mode All others Lock Step mode SPNU563A – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 298: Logicpd Pscon Diagnostic Compare Status Register 1 (Lpddcstat1)
Bit 0 for PD2. Read in User and Privileged Mode. Writes have no effect. Self-test is ongoing if self-test mode is entered. Self-test is complete. Power Management Module (PMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 299: Logicpd Pscon Diagnostic Compare Status Register 2 (Lpddcstat2)
Bit 2 for PD4, Bit 1 for PD3, Bit 0 for PD2. Read in User and Privileged Mode. Writes have no effect. Self-test passed. Self-test failed. SPNU563A – March 2018 Power Management Module (PMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 300: Isolation Diagnostic Status Register (Isodiagstat)
Read in User and Privileged Mode. Writes have no effect. Isolation is enabled for corresponding power domain Isolation is disabled for corresponding power domain Power Management Module (PMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 301: I/O Multiplexing And Control Module (Iomm)
Control of Multiplexed Outputs ................Control of Multiplexed Inputs ............... Control of Special Multiplexed Options ....................Safety Features ....................IOMM Registers SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 302: Overview
N17. – If the application sets 16, 17 and 18, then the default function will be selected for output on N17. I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 303: Control Of Multiplexed Inputs
Some signals, like eCAPx and eQEPx, are by default mapped to an unavailable ball on the 337ZWT package. The alternate terminals have to be used, in this case, in order to use these signals. SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 304 ETMDATA[10] 11[24] EMIF_ADDR[03] 11[25] 140h ETMDATA[11] 12[0] EMIF_ADDR[02] 12[1] ETMDATA[12] 12[8] EMIF_BA[0] 12[9] ETMDATA[13] 12[16] EMIF_nOE 12[17] ETMDATA[14] 12[24] EMIF_nDQM[1] 12[25] I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 305 21[8] MIBSPI1SOMI[1] 21[9] MII_TXD[2] 21[10] ECAP6 21[13] MIBSPI1NCS[1] 21[16] MII_COL 21[18] N2HET1[17] 21[19] eQEP1S 21[21] MIBSPI1NCS[2] 21[24] MDIO 21[26] N2HET1[19] 21[27] SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 306 30[9] N2HET2[16] 30[11] ePWM7A 30[13] N2HET1[10] 30[16] MIBSPI4NCS[4] 30[17] MII_TX_CLK 30[18] nTZ1_3 30[21] N2HET1[11] 30[24] MIBSPI3NCS[4] 30[25] N2HET2[18] 30[27] EPWM1SYNCO 30[29] I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 307 MIBSPI2NCS[0] 37[12] Selecting N2HET1_NDIS or N2HET2_NDIS forces the pin to a high-impedance state and changes the pull type to pull up. SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 308 Control of Multiplexed Inputs www.ti.com I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 309 PINMMR90[8] PINMMR90[9] MII_RXCLK PINMMR90[16] PINMMR90[17] MII_RXD[0] PINMMR90[24] PINMMR90[25] 27Ch MII_RXD[1] PINMMR91[0] PINMMR91[1] MII_RXD[2] PINMMR91[8] PINMMR91[9] MII_RXD[3] PINMMR91[16] PINMMR91[17] MII_TX_CLK PINMMR91[24] PINMMR91[25] SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 310 PINMMR98[0] PINMMR98[1] N2HET2[18] PINMMR98[8] PINMMR98[9] N2HET2[20] PINMMR98[16] PINMMR98[17] N2HET2[22] PINMMR98[24] PINMMR98[25] 29Ch nTZ1_1 PINMMR99[0] PINMMR99[1] nTZ1_2 PINMMR99[8] PINMMR99[9] nTZ1_3 PINMMR99[16] PINMMR99[17] I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 311 GIO signal. Figure 6-3. Input Multiplexing Example SCI4 EMIF Not (PINMMR92[0]=0 and PINMMR92[1]=1) N2HET1[17]/EMIF_nOE/SCI4RX N2HET1[17]_IN N2HET1 MIBSPI1NCS[1]/MII_COL/N2HET1[17]/eQEP1S MIBSPI1 Ethernet eQEP1 SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 312: Control Of Special Multiplexed Options
Trip Zone 4 Select 3B0h PINMMR168[0] PINMMR168[1] PINMMR168[2] ePWM6 Trip Zone 4 Select PINMMR168[8] PINMMR168[9] PINMMR168[10] ePWM7 Trip Zone 4 Select PINMMR168[16] PINMMR168[17] PINMMR168[18] I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 313 PINMMR178[16] GIOB[7] DMA Request Select PINMMR178[24] NHET2 Pin Disable Select 3DCh PINMMR179[0] PINMMR179[1] Section 6.5.6 NHET1 Pin Disable Select PINMMR179[8] PINMMR179[9] SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 314: Control Of Sdram Clock (Emif_Clk)
PINMMR162[8] = x PINMMR162[9] = x GIOB[1] PINMMR162[8] = 1 PINMMR162[9] = 0 N2HET2[13] PINMMR162[8] = 0 PINMMR162[9] = 1 ePWM_AB I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 315: Control For Adc Event Trigger Signal Generation From Epwmx Modules
I/O multiplexing module are used to control the logic for generation of the ePWM_A1, ePWM_A2, ePWM_AB, and ePWM_B signals from these ePWMx_SOCA and ePWMx_SOCB signals. SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 316 EPWM4SOCA ePWM4 EPWM4SOCB module EPWM5SOCA ePWM5 EPWM5SOCB module EPWM6SOCA ePWM6 EPWM6SOCB module EPWM7SOCA ePWM7 EPWM7SOCB module ePWM_B ePWM_A1 ePWM_A2 ePWM_AB I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 317 • PINMMR165[16] defines the value of SOC7A_SEL. This bit is set by default and can be cleared by the application. SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 318: Control For Generating Interrupt Upon External Fault Indication To N2Hetx
Figure 6-5. GIOA[5] and N2HET1_NDIS Input Multiplexing Scheme PINMMR179[8]=1 and PINMMR179[9]=0 N2HET2[01]/N2HET1_NDIS PIN_nDISABLE N2HET1 GIOA[5]/EXTCLKIN/ePWM1A ETMTRACECLKIN/EXTCLKIN2/GIOA[5] PINMMR85[0]=1 and PINMMR85[1]=0 I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 319 N2HET2 and this will be compatible to other TMS570LSxx family of microcontrollers which have this available feature. SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 320: Control For Synchronizing Time Bases For All Epwmx Modules
Figure 6-7. Synchronizing ePWMx Modules to N2HET1 Time-Base EXT_LOOP_SYNC N2HET1_LOOP_SYNC N2HET1 N2HET2 PINMMR165[24]=0 and PINMMR165[25]=1 2 VCLK3 cycles Pulse Stretch SYNCI ePWM1SYNCI ePWM1 Double synch ePWM1_SYNCI 6-bit counter I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 321: Control For Input Connections To Epwmx Modules
PINMMR173[1] = 1 PINMMR173[2] = 1 PINMMR173[8] = 0 PINMMR173[9:8] = "00" ePWM1_SYNCI PINMMR173[8] = 1 PINMMR173[9] = 1 PINMMR173[10] = 1 SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 322: Control For Input Connections To Ecapx Modules
PINMMR169[25] = 1 PINMMR170[0] = 0 eCAP5 PINMMR170[0] = 0 PINMMR170[1] = 1 PINMMR170[8] = 0 eCAP6 PINMMR170[8] = 0 PINMMR170[9] = 1 I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 323: Control For Input Connections To Eqepx Modules
PINMMR171[25] = 1 PINMMR172[0] = 0 eQEP2I PINMMR172[0] = 1 PINMMR172[1] = 1 PINMMR172[8] = 0 eQEP2S PINMMR172[8] = 1 PINMMR172[9] = 1 SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 324 I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 325: Selecting Gio Port For External Dma Request
PINMMR176[8] GIOA[6] PINMMR176[16] GIOA[7] PINMMR176[24] GIOB[0] PINMMR177[0] GIOB[1] PINMMR177[8] GIOB[2] PINMMR177[16] GIOB[3] PINMMR177[24] GIOB[4] PINMMR178[0] GIOB[5] PINMMR178[8] GIOB[6] PINMMR178[16] GIOB[7] PINMMR178[24] SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 326: Temperature Sensor Selection
AD2CHNSEL(30) = 1 AD2IN[30] PINMMR174(0) =1 PINMMR174(1) = 0 AD1CHNSEL is configured inside the MibADC1 Wrapper. AD2CHNSEL is configured inside the MibADC2 Wrapper. I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 327: Safety Features
• Protection Error – occurs when the CPU writes to an IOMM register while not in a privileged mode of operation. SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 328: Iomm Registers
E84h Module Id 15-11 REV RTL RTL Revision 10-8 REV MAJOR Major Revision REV CUSTOM Custom Revision REV MINOR Minor Revision I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 329: Boot_Reg: Boot Mode Register
Reads return 0, writes have no effect. ENDIAN Device endianness. Device is configured in little-endian mode. Device is configured in big-endian mode. SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 330: Kick_Reg0: Kicker Register
Kicker 1 Register. The value 95A4 F1E0h must be written to the KICK1 as part of the process to unlock the CPU write access to the PINMMRnn registers. I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 331: Err_Raw_Status_Reg: Error Raw Status / Set Register
Read: Protection Error has not occurred. Write: Writing 0 has no effect. Read: Protection Error has been detected. Write: Protection Error status is set. SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 332: Err_Enabled_Status_Reg: Error Enabled Status / Clear Register
Read: Protection Error Signaling is disabled. Write: Writing 0 has no effect. Read: Protection Error Signaling is enabled. Write: Protection Error status is cleared. I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 333: Err_Enable_Reg: Error Signaling Enable Register
Read: Protection Error Signaling is disabled. Write: Writing 0 has no effect. Read: Protection Error Signaling is enabled. Write: Protection Error Signaling is enabled. SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 334: Err_Enable_Clr_Reg: Error Signaling Enable Clear Register
Reads return 0, writes have no effect. FAULT_ADDR Fault Address. The fault address offset in case of an address error or a protection error condition. I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 335: Fault_Status_Reg: Fault Status Register
Type of fault detected. No fault User execute fault User write fault User read fault Supervisor execute fault Supervisor write fault Supervisor read fault SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 336: Fault_Clear_Reg: Fault Clear Register
Each of these byte-fields control the functionality on a given ball/pin. Please refer to Table 6-1 for a list of multiplexed signals. 23-16 PINMMRx[23-16] 15-8 PINMMRx[15-8] PINMMRx[7-0] I/O Multiplexing and Control Module (IOMM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 337: Pinmmrnn: Input Pin Multiplexing Control Registers
Each of these byte-fields control the functionality on a given ball/pin. Please refer to Table 6-3 for a list of multiplexed signals. 23-16 PINMMRx[23-16] 15-8 PINMMRx[15-8] PINMMRx[7-0] SPNU563A – March 2018 I/O Multiplexing and Control Module (IOMM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 338: F021 Level 2 Flash Module Controller (L2Fmc)
............... Parameter Overlay Module (POM) ................Summary of L2FMC Errors ..................7.10 Flash Control Registers ..................7.11 POM Control Registers F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 339: Overview
Flash can be electrically programmed and erased many times to ease code development. Refer to the following documents for support on how to initialize and use the on-chip Flash and its API: • F021 (Texas Instruments 65nm Flash) Flash API Reference Guide (SPNU501) 7.1.1 Features •...
Page 340: F021 Flash Tools
POM - Parameter Overlay Module provides a method to remap the Flash when there is a need to have different values in the Flash contents without actually erasing and reprogramming the Flash. 7.1.3 F021 Flash Tools Texas Instruments provides the following tools for F021 Flash: • nowECC Generation Tool - to generate the Flash ECC from the Flash data.
Page 341: Secded
The ECC encoding is shown in Table 7-1. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 342 Each ECC[x] bit represents the XOR of all the address and data bits marked with x in the same row. F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 343: Syndrome Table: Decode To Bit In Error
0 0 1 0 0 1 0 1 1 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 1 Bit[0] SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 344: Syndrome Table: An Alternate Method
E0x - Single-bit ECC error, correctable • Dxx - Single-bit data error, correctable • D - Double-bit error, uncorrectable • M - Multi-bit errors, uncorrectable F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 345: Memory Map
64 – bit data word 2 ECC2 0xF0100001 0xF0200008 64 – bit data word 1 ECC1 0xF0200000 64 – bit data word 0 0xF0100000 ECC0 SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 346: Otp Memory
Bank TI OTP Address F008 0158h F008 2158h F008 4158h F008 6158h F008 8158h F008 A158h F008 C158h F008 E158h F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 347 Table 7-7. TI OTP Bank 0 LPO Trim and Max HCLK Information Field Descriptions Field Description 31-24 HFLPO_TRIM HF LPO Trim Solution 23-16 LFLPO_TRIM LF LPO Trim Solution 15-0 MAX_GCLK Maximum GCLK1 Speed SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 348 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E S3TEMP1VAL S3TEMP1 S3TEMP2VAL S3TEMP2 S3TEMP3VAL S3TEMP3 0xFFFF 0xFFFF LEGEND: R = Read only F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 349 0x04 0x08 0x0C 0x12345678 0x9ABCDEF1 0x12345678 0x9ABCDEF3 LEGEND: R = Read only, * ECC is calculated for the value 0x123456789ABCDEF0 SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 350: Power On, Power Off Considerations
Diagnostic mode is disabled. Same as DIAG_EN_KEY not equal to 5h. Address Tag Register test mode ECC Data Correction Diagnostic test mode Others Other Combinations Reserved F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 351 NOTE: You should pre-load the registers with the test values with DIAG_TRIG = 0. After all test values are written, the DIAG_TRIG should then be set high to validate the diagnostic result. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 352: Diagnostic Mode Summary
ECC single-bit or error. Please refer to the FEMU_DxSW Diagnostic test multi-bit error. data manual to find mode group and channel number. F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 353: Secded Software Diagnostic
5. Write to the POMREGSIZE0.SIZE (offset 208h) a value of Ch. 6. Finally write to the POMGLBCTRL.ON_OFF to Ah. 7. End of sequence. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 354: Summary Of L2Fmc Errors
FEDAC_PxSTATUS. POM Idle State parity error MCMD_PAR_ERR Soft Errors in high integrity bits carrying FEDAC_GBLSTATUS. Implicit read data RCR_ERR F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 355: Flash Control Registers
FSM Sector Register 1 Section 7.10.33 2C4h FSM_SECTOR2 FSM Sector Register 2 Section 7.10.34 400h FCFG_BANK Flash Bank Configuration Register Section 7.10.35 SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 356: Flash Read Control Register (Frdcntl)
Prefetch Mode is enabled. (Recommended) PFUENA Prefetch Enable for Port A Prefetch Mode is disabled. Prefetch Mode is enabled. (Recommended) F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 357: Read Margin Control Register (Fsprd)
Read Margin 1 Mode is enabled. Read Margin 0 Read Margin 0 Mode is disabled. Read Margin 0 Mode is enabled. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 358: Eeprom Error Correction Control Register (Ee_Fedacctrl1)
Allow the condition of all data bits and ECC bits to be 0. Reserved Reads return 0. Writes have no effect. F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 359: Flash Port A Error And Status Register (Fedac_Pastatus)
This error is routed to the ESM. Refer to the device data manual to find the specific group and channel on which it is routed. Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 360: Flash Port B Error And Status Register (Fedac_Pbstatus)
This error is routed to the ESM. Refer to the device data manual to find the specific group and channel on which it is routed. Reserved Reads return 0. Writes have no effect. F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 361: Flash Global Error And Status Register (Fedac_Gblstatus)
This error is routed to the ESM. Refer to the device data manual to find the group and channel on which it is routed. 12-0 Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 362: Flash Error Detection And Correction Sector Disable Register (Fedacsdis)
ID bits, then no sector is disabled by disable ID 0. F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 363: Primary Address Tag Register (Fprim_Add_Tag)
The register clears when an address tag error is found and when leaving DIAG_MODE 5. Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 364: Flash Bank Protection Register (Fbprot)
The corresponding numbered sector is disabled for program or erase access. The corresponding numbered sector is enabled for program or erase access. F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 365: Flash Bank Busy Register (Fbbusy)
Flash wrapper design. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 366: Flash Bank Power Mode Register (Fbpwrmode)
Bank standby mode Reserved Bank active mode BANKPWR0 Bank 0 Power Mode. Bank sleep mode Bank standby mode Reserved Bank active mode F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 367: Flash Bank/Pump Ready Register (Fbprdy)
Bank 0 (bit 0) and Bank 1 (bit 1) Ready Status Bank is not ready for Flash access. Bank is ready for Flash access. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 368: Flash Pump Access Control Register 1 (Fpac1)
Reads return 0. Writes have no effect. PUMPPWR Flash Charge Pump Fallback Power Mode Sleep (all pump circuits are disabled) Active (all pump circuits are active) F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 369: Flash Module Access Control Register (Fmac)
BANK and read back the value to see if what was written can be read back. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 370: Flash Module Status Register (Fmstat)
Erase Sector command. During Precondition verify command, this flag is set immediately if a Flash bit is found to be 1. F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 371 1s. A SLOCK error will occur if attempting to do a sector erase with either BSE is cleared or SECT_ERASED is set. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 372: Eeprom Emulation Data Msw Register (Femu_Dmsw)
This register is used in diagnostic mode 7 to XOR the lower 32 bits of the data being delivered to the bus master. F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 373: Eeprom Emulation Ecc Register (Femu_Ecc)
All other values Writes to EE_FEDACCTRL1 are ignored. It is recommended to leave this register as 55AAh when not writing to the FEDACCTRL1 register. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 374: Diagnostic Control Register (Fdiagctrl)
Diagnostic mode is disabled. This is the same as DIAG_EN_KEY is not equal to 5h. Address Tag Register test mode (see Section 7.7.2.1). ECC Data Correction Diagnostic test mode (see Section 7.7.2.2). F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 375: Raw Address Register (Fraw_Addr)
31:3. The lower 5 bits are not compared during the diagnostic. Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 376: Parity Override Register (Fpar_Ovr)
All other values Any other value causes the module to use the global system parity bit in the system register DEVCR1. Reserved Reads return 0. Writes have no effect. F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 377: Reset Configuration Valid Register (Rcr_Valid)
This can occur due to soft error in internal logic. It is NOT recommended to modify this register unless a crossbar diagnostic is being performed. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 378: Flash Error Detection And Correction Sector Disable Register 2 (Fedacsdis2)
ID bits, then no sector is disabled by disable ID 2. F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 379: Lower Word Of Reset Configuration Read Register (Rcr_Value0)
RCR_VALUE Varies with device Value of the upper 32 bits of the implicit read. Valid only if RCR_VALID is set. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 380: Fsm Register Write Enable Register (Fsm_Wr_Ena)
Replaces the RWAIT count in the EEPROM register. The same formulas that apply to RWAIT apply to EWAIT in the EEPROM bank. 15-0 Reserved Reads return 0. Writes have no effect. F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 381: Fsm Sector Register 1 (Fsm_Sector1)
0 to 1. During bank erase, each sector whose corresponding bit is 1 will not be erased. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 382: Flash Bank Configuration Register (Fcfg_Bank)
The 288 bits includes 256 data bits and 32 ECC bits. Reserved Writes have no effect. F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 383: Pom Control Registers
21-4 Reserved Reads return 0. Writes have no effect. ON_OFF POM enable except Ah POM is disabled. POM is enabled. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 384: Pom Revision Id Register (Pomrev)
Parity error on POM Port A remap request has NOT occurred. Parity error on POM Port A remap request has occurred. Reserved Reads return 0. Writes have no effect. F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 385: Pom Region Start Address Register (Pomprogstartx)
Reads return 0. Writes have no effect. 22-6 STARTADDRESS Start address of the program memory region. Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 F021 Level 2 Flash Module Controller (L2FMC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 386: Pom Region Size Register (Pomregsizex)
Reads return 0. Writes have no effect. SIZE Region is disabled. 64 bytes 128 bytes 128K bytes 256K bytes Eh-Fh Reserved F021 Level 2 Flash Module Controller (L2FMC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 387: Level 2 Ram (L2Ramw) Module
This chapter describes the Level II RAM (L2RAM) module..........................Topic Page ......................Overview ..................... Module Operation ................Control and Status Registers SPNU563A – March 2018 Level 2 RAM (L2RAMW) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 388: Overview
64-bit aligned. Writes to the ECC space must also first be enabled via the RAM Control Register (RAMCTRL). Accesses to the ECC space are not traced out to the RAM Trace Port (RTP). Level 2 RAM (L2RAMW) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 389: Safety Features
NOTE: The RAM Error Status Register does not indicate ECC errors that are detected by the Cortex R5F CPU. These errors and handled and flagged in the R5F registers SPNU563A – March 2018 Level 2 RAM (L2RAMW) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 390 Group 3, bus error Level 2 RAM illegal address error n/a (bus error only) Memory initialization error MIE (13) n/a (bus error only) Level 2 RAM (L2RAMW) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 391 L2RAMW and ECC memory. SPNU563A – March 2018 Level 2 RAM (L2RAMW) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 392: L2Ramw Auto-Initialization
The diagnostic errors will also be sent to ESM group 2 as "uncorrectable error type B". Level 2 RAM (L2RAMW) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 393: Control And Status Registers
Data is blocked from being traced out to the trace modules for emulation mode accesses. 29-28 Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 Level 2 RAM (L2RAMW) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 394 Write Operations). All other ECC handling is done by the R5F CPU. ECC error checking cannot be disabled on the R5F CPU. ECC detection is disabled. All other values ECC detection is enabled. Level 2 RAM (L2RAMW) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 395: L2Ramw Error Status Register (Ramerrstatus)
1 to it before any new error can be generated. An address decode error did not occur during scrubbing write back. An address decode error occurred during scrubbing write back. SPNU563A – March 2018 Level 2 RAM (L2RAMW) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 396 This bit must be cleared by writing a 1 to it before any new error can be generated. An error did not occur. An error occurred. Level 2 RAM (L2RAMW) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 397 1 to it in order to clear the interrupt request and to enable subsequent single- bit error interrupt generation. An error did not occur. An error occurred. SPNU563A – March 2018 Level 2 RAM (L2RAMW) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 398: L2Ramw Diagnostic Data Vector High Register (Diag_Data_Vector_H)
This register is the lower 32 bits. This register is used in conjunction with the RAMTEST register to perform diagnostic tests. See Section 8.2.6 details on how to start a diagnostic test. Level 2 RAM (L2RAMW) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 399: L2Ramw Diagnostic Ecc Vector Register (Diag_Ecc)
DIAG_DATA_VECTOR_L registers to form a data/ECC pair in the diagnostic ECC checking test. See Section 8.2.6 for details on how to start a diagnostic test. SPNU563A – March 2018 Level 2 RAM (L2RAMW) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 400: L2Ramw Ram Test Mode Control Register (Ramtest)
DIAG_DATA_VECTOR_H registers. The functional path comparison is disabled when test mode is enabled. Test mode is enabled. All other values Test mode is disabled. Level 2 RAM (L2RAMW) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 401: L2Ramw Ram Address Decode Vector Test Register (Ramaddrdec_Vect)
RAM Chip Select. This field is used to store the RAM chip select value for the redundant address decode and compare logic. The stored value is passed as test stimulus for the built-in test scheme. SPNU563A – March 2018 Level 2 RAM (L2RAMW) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 402: L2Ramw Memory Initialization Domain Register (Meminit_Domain)
Bit 7: enable bit for power domain 7. Enable the memory in this power domain to be initialized. Disable the memory in this power domain from being initialized. Level 2 RAM (L2RAMW) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 403: L2Ramw Bank To Domain Mapping Register0 (Bank_Domain_Map0)
Reads return 0. Writes have no effect. BANK0_MAP 0-7h This 3-bit field allows the software to read the memory power domain number that bank 0 is associated. SPNU563A – March 2018 Level 2 RAM (L2RAMW) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 404: L2Ramw Bank To Domain Mapping Register1 (Bank_Domain_Map1)
Reads return 0. Writes have no effect. BANK8_MAP 0-7h This 3-bit field allows the software to read the memory power domain number that bank 8 is associated. Level 2 RAM (L2RAMW) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 405: Programmable Built-In Self-Test (Pbist) Module
RAM Grouping and Algorithm ...................... PBIST Flow ............ Memory Test Algorithms on the On-chip ROM ................... PBIST Control Registers ................PBIST Configuration Example SPNU563A – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 406: Overview
Figure 9-1. PBIST Block Diagram Host CPU Control Interface Memory Configurations, PBIST PBIST Controller Algorithms, System Backgrouns Memory Data Peripheral Path Memories Data Logger Programmable Built-In Self-Test (PBIST) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 407: Ram Grouping And Algorithm
RAM groups with the background patterns used for the particular algorithm. NOTE: March13 is the most recommended algorithm for the memory self-test. SPNU563A – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 408: Pbist Flow
Disable pbist clocks and ROM clock by writing PACT = 0 Disable PBIST Test by writing MSTGCR = 0x05 PBIST Selftest Done Programmable Built-In Self-Test (PBIST) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 409: Pbist Sequence
Disable the PBIST internal clocks by writing a 0 to the PACT register. b. Disable the PBIST self-test by writing a value of 5h to bits 3:0 of the MSTGCR in the system module. SPNU563A – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 410 ; You must issue an ISB instruction to flush the pipeline. ; This ensures that all subsequent instruction fetches ; see the effect of enabling the instruction cache Programmable Built-In Self-Test (PBIST) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 411: Memory Test Algorithms On The On-Chip Rom
– Address decoder faults – Stuck-At faults – Coupled faults – State coupling faults – Parametric faults – Write recovery faults – Read/write logic faults SPNU563A – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 412: Pbist Control Registers
ROM Algorithm Mask Register Section 9.5.11 1C8h RINFOL RAM Info Mask Lower Register Section 9.5.12 1CCh RINFOU RAM Info Mask Upper Register Section 9.5.13 Programmable Built-In Self-Test (PBIST) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 413: Ram Configuration Register (Ramt)
Note: In the current version of the PBIST, only 5 bits are used for RDS. 15-8 Data Width Register Sense Margin Select Register Pipeline Latency Select RAM Latency Select SPNU563A – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 414: Datalogger Register (Dlr)
• DLR4: Config access mode This mode, when set, indicates the CPU is being used to access PBIST. Programmable Built-In Self-Test (PBIST) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 415: Pbist Activate/Clock Enable Register (Pact)
As long as this bit is 0, any access to the PBIST will not go through and the PBIST will remain in an almost zero-power mode. SPNU563A – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 416: Pbist Id Register
Reads return 0. Writes have no effect. PBIST ID This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. Programmable Built-In Self-Test (PBIST) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 417: Override Register (Over)
2. Only memories that are valid for all algorithms enabled via the ALGO register are selected. If the above two requirements are not met, the memory self-test will fail. SPNU563A – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 418: Fail Status Fail Register (Fsrf0)
Fail Status 0. This bit would be cleared by reset of the module using MSTGCR register in system module. No failure occurred. Failure occurred on port 0. Programmable Built-In Self-Test (PBIST) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 419: Fail Status Count Registers (Fsrc0 And Fsrc1)
31-8 Reserved Reads return 0. Writes have no effect. FSRC1 Fail Status Count 1. Indicates the number of failures on port 1. SPNU563A – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 420: Fail Status Address Registers (Fsra0 And Fsra1)
31-16 Reserved Reads return 0. Writes have no effect. 15-0 FSRA1 Fail Status Address 1. Contains the address of the first failure. Programmable Built-In Self-Test (PBIST) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 421: Fail Status Data Registers (Fsrdl0 And Fsrdl1)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9-13. Fail Status Data Register 1 (FSRDL1) Field Descriptions Field Description 31-0 FSRDL1 Failure data on port 1. SPNU563A – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 422: Rom Mask Register (Rom)
Only RAM Group information from ROM. Only Algorithm information from ROM. Both Algorithm and RAM Group information from ROM. This option should be selected for application self-test. Programmable Built-In Self-Test (PBIST) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 423: Rom Algorithm Mask Register (Algo)
None of the algorithms are selected. NOTE: Please refer to Table 2-6 for available algorithms and the memories on which each algorithm can be run. SPNU563A – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 424: Ram Info Mask Lower Register (Rinfol)
Selects RAM Group 1 for PBIST run. 31-0 None of the RAM Groups 1 to 32 are selected. NOTE: Please refer to Table 2-5 for RAM info groups. Programmable Built-In Self-Test (PBIST) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 425: Ram Info Mask Upper Register (Rinfou)
RAM Group 33 is not selected. Selects RAM Group 33 for PBIST run. 31-0 None of RAM Groups 33 to 64 are selected. SPNU563A – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 426: Pbist Configuration Example
In case there is no failure (FSRF0 = 0), the memory self-test is completed. a. Disable the PBIST internal clocks. PACT = 0 b. Disable the PBIST self-test. MSTGCR[3:0] = 0x5 Programmable Built-In Self-Test (PBIST) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 427: Example 2 : Configuration Of Pbist Controller To Run Self-Test On All Ram Groups
In case there is no failure (FSRF0 = 0), the Memory self-test is completed. a. Disable the PBIST internal clocks. PACT = 0 b. Disable the PBIST self-test. MSTGCR[3:0] = 0x5 SPNU563A – March 2018 Programmable Built-In Self-Test (PBIST) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 428: Self-Test Controller (Stc) Module
............10.7 STC2 (nHET) Test Coverage and Duration ..................10.8 STC Control Registers ................10.9 STC Configuration Example ................ 10.10 Self-Test Controller Diagnostics Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 429: General Description
STC1, GCLK1 is divided down; for STC2, VCLK2 is divided down to generate STCCLK. • Low-frequency shift. Programmable clock divider register inside STC to reduce the shift frequency in order to reduce the shift power. SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 430: Terminology
Peripheral Bus (VBUSP) Interface. This block controls the reseeding (reloading the existing seed of the PRPG) in the LBIST controller. Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 431 SEG0 Bisted CPU1 and CPU2 including STC REG STC_BYPASS/ DBIST BLOCK ATE Interface SEG1 Bisted SCU VBUSP including DBIST Inteface Test Controller SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 432 CPU1 Cortex-R5F (Bisted CORE) DBIST CNTRL1 STC REG STC_BYPASS/ BLOCK ATE Interface Compare DBIST CNTRL2 CPU2 Cortex-R5F VBUSP (Bisted CORE) Inteface Test Controller Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 433 BLK2 Interface Controller misr_out COMP BLK1 nHET1 DBIST CNTRL1 STC REG STC_BYPASS/ BLOCK ATE Interface DBIST CNTRL2 nHET2 VBUSP Inteface Test Controller SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 434 (Bisted CORE) Inteface Test Controller Modules highlighted in red will not be enabled for test while testing CORE1 only in a redundant system. Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 435 (Bisted CORE) Inteface Test Controller Modules highlighted in red will not be enabled for test while testing CORE2 only in a redundant system. SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 436: Stc Module Assignments
µSCU (ACP Block) GCLK1 None STC2 Segment 0 nHET1 and nHET2 VCLK2 Segment 0 allows nHET1 and nHET2 to be tested in parallel or individually. Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 437: Stc Programmers Flow
Read Self test status registers. Self-test Done? Retrieve MUT state if required. The steps shown in red can be bypassed for self-test with single core only. SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 438: Application Self-Test Flow
NOTE: Check all reset source flags in the SYSESR register after a CPU BIST execution. If a flag in addition to CPU reset is set, clear the CPU reset flag and service the other reset sources accordingly. Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 439: Entering Cpu Idle Mode
SYSESR register bits cleared. SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 440 The STC Updates the STC status registers Intervals done and generates CPU reset and stc_testerr_o End of Self Test (Disable the STC_ENA Key) Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 441: Stc1 Segment 0 (Cpu) Test Coverage And Duration
52128 89.10 53757 89.23 55386 89.41 57015 89.55 58644 89.70 60273 89.83 61902 89.96 63531 90.10 65160 90.23 66789 90.33 68418 90.43 70047 SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 442 128691 93.36 130320 93.42 131949 93.48 133578 93.55 135207 93.60 136836 93.66 138465 93.71 140094 93.76 141723 93.81 143352 93.86 144981 93.91 146610 Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 443 @ GCLK1 = 300 MHz Number of Intervals Coverage STCCLK = 110 MHz STCCLK = 100 MHz >90% 592.4 µS 651.6 µS >95% 1.8511 mS 2.036 mS SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 444: Stc1 Segment 1 (Μscu) Test Coverage And Duration
15015 92.02 16380 92.37 17745 92.66 19110 92.87 20475 93.04 21840 93.26 23205 93.47 24570 93.67 25935 93.82 27300 93.96 28665 94.12 30030 Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 445 @ VCLK = 150 MHz Number of Intervals Coverage STCCLK = 110 MHz STCCLK = 75 MHz >90% 111.68 µS 163.8 µS >96% 707.3 µS 1.038 mS SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 446: Stc Control Registers
STC Current ROM Address Register - CORE2 Section 10.8.11 STCCLKDIV STC Clock Divider Register Section 10.8.12 STCSEGPLR STC Segment First Preload Register Section 10.8.13 Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 447: Stc Global Control Register 0 (Stcgcr0)
0. This bit gets reset after the completion of a self-test run. Continue STC run from the previous interval. Restart STC run from interval 0. 2h-3h Reserved SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 448: Stc Global Control Register 1 (Stcgcr1)
Reads return 0. Writes have no effect. STC_ENA Self-test run enable key. Self-test run is enabled. All other values Self-test run is disabled. Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 449: Self-Test Run Timeout Counter Preload Register (Stctpr)
The preload count value gets loaded into the self-test time out down counter whenever a self-test run is initiated (STC_KEY is enabled) and gets disabled on completion of a self-test run. SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 450: Stc Current Rom Address Register - Core1 (Stccaddr1)
Interval Number This specifies the last executed interval number for Core1 in case of self-test being run on Segment0 or any other segments. Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 451: Self-Test Global Status Register (Stcgstat)
3. When a timeout failure occurs Reset is generated to the CPU on which the STC run is being performed when TEST_DONE goes high (the test is completed). SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 452: Self-Test Fail Status Register (Stcfstat)
Self-test run failed due to MISR mismatch for CORE2. CORE1_FAIL CORE1 failure info for segment 0 only. No MISR mismatch for CORE1. Self-test run failed due to MISR mismatch for CORE1. Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 453: Core1 Current Misr Registers (Core1_Curmisr[3:0])
This register contains the MISR data from the CORE1 for the most recent interval in case of segment 0 and all other segments. This value is compared with the GOLDEN MISR value copied from ROM. SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 454: Core2 Current Misr Registers (Core2_Curmisr[3:0])
This register contains the MISR data from the CORE2 for the most recent interval in case of segment 0l. This value is compared with the GOLDEN MISR value copied from ROM. Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 455: Signature Compare Self-Check Register (Stcscscr)
This register reflects the current ROM address (address or micro code load) accessed during self-test Segment0 -Core2. This is the current value of the STC program counter. SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 456: Stc Clock Prescalar Register (Stcclkdiv)
Division ratio of segment 1 will be n+1. STCCLK clock will be divided by (n+1) for segment 1. 15-0 Reserved Reads return 0. Writes have no effect. Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 457: Segment Interval Preload Register (Stcsegplr)
Preload the address of the 1st interval for Segment 0. Preload the address of the 1st interval for Segment 1. All other values Reserved SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 458: Stc Configuration Example
In case there is no failure (TEST_DONE = 1 and TEST_FAIL = 0), the CPU self-test is completed successfully. • Recover the CPU status, configuration registers and continue the application software. Self-Test Controller (STC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 459: Self-Test Controller Diagnostics
TEST_FAIL bit will be cleared in the STCGSTAT register. After the diagnostics, the application can continue with the self-test as described in Section 10.4. SPNU563A – March 2018 Self-Test Controller (STC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 460: System Memory Protection Unit (Nmpu)
This chapter describes the System Memory Protection Unit (NMPU)..........................Topic Page ......................11.1 Overview ..................... 11.2 Module Operation .................... 11.3 How to Use NMPU ....................11.4 NMPU Registers System Memory Protection Unit (NMPU) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 461: Overview
Provide a lock mechanism to avoid unintentional changes to NMPU control registers. • Provide diagnostic capability to check the MPU region access permission logic. SPNU563A – March 2018 System Memory Protection Unit (NMPU) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 462: Block Diagram
Block Diag mode control Error Pulse Error Priority Response Address and Access Generation Permission Comparator 7 fail Priority Output Bus Interconnect Interface System Memory Protection Unit (NMPU) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 463: Module Operation
SPNU563A – March 2018 System Memory Protection Unit (NMPU) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 464 Update ERRSTAT and Update ERRSTAT and ERRADDR. Bus Output to ERRADDR. Set BGERR/Redirect Access Interconnect Set APERR/Redirect Access to NULL Slave to NULL Slave System Memory Protection Unit (NMPU) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 465: Diagnostic Mode
SPNU563A – March 2018 System Memory Protection Unit (NMPU) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 466: How To Use Nmpu
10KB of the system RAM. The rest of the system RAM is reserved for other tasks in which the DMA should not interfere with. System Memory Protection Unit (NMPU) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 467 6. Program the MPUREGBASE register (Section 11.4.10) to set the base address for the particular MPU region number that was set in step 5. SPNU563A – March 2018 System Memory Protection Unit (NMPU) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 468: How To Use Diagnostics
NMPU needs to have the hardware logic for run-time diagnostics. This logic is implemented using 1oo1D safety architecture. System Memory Protection Unit (NMPU) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 469 15. User enables bus master. Please follow the bus master TRM on how to enable the bus interface. it will be different from one bus master to another. SPNU563A – March 2018 System Memory Protection Unit (NMPU) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 470 17. Restart the bus master functional operation. Please follow the bus master TRM on how to enable the bus interface. it will be different from one bus master to another. System Memory Protection Unit (NMPU) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 471: Nmpu Registers
MPU Region Size and Enable Register Section 11.4.11 MPUREGACR MPU Region Access Control Register Section 11.4.12 MPUREGNUM MPU Region Number Register Section 11.4.13 SPNU563A – March 2018 System Memory Protection Unit (NMPU) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 472: Mpu Revision Id Register (Mpurev)
29-28 Reserved Reserved. Reads return 0. 27-16 FUNC A0Ch Indicates functionally equivalent module family. This value is dedicated to Hercules family from other general Texas Instruments MCU or MPU family. 15-11 RTL version number. 10-8 MAJOR Major revision number. CUSTOM Indicates device-specific implementation.
Page 473: Mpu Diagnostics Control Register (Mpudiagctrl)
Write in Privilege: Diagnostics mode is disabled. Diagnostics mode is enabled. All other values Reserved. The bits remain unchanged. Reserved Reserved. Reads return 0. SPNU563A – March 2018 System Memory Protection Unit (NMPU) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 474: Mpu Diagnostic Address Register (Mpudiagaddr)
There was no memory access to addresses that are outside all the enabled MPU regions. MPU compare fail generated because of access to an address that is outside all the enabled MPU regions. System Memory Protection Unit (NMPU) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 475 No MPU compare fail was detected. At least one MPU compare fail was detected. Write in Privilege: Reserved. The bit remains unchanged. Clears the bit. SPNU563A – March 2018 System Memory Protection Unit (NMPU) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 476: Mpu Error Address Register (Mpuerraddr)
Read: Returns current value of MPUENA. Write in Privilege: Memory protection is disabled. Memory protection is enabled. All other values Reserved. The bits remain unchanged. System Memory Protection Unit (NMPU) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 477: Mpu Control Register 2 (Mpuctrl2)
Error pulse output to ESM is disabled. Error pulse output to ESM is enabled. All other values Reserved. The bits remain unchanged. SPNU563A – March 2018 System Memory Protection Unit (NMPU) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 478: Mpu Type Register (Mputype)
6 MPU regions are implemented. 7 MPU regions are implemented. 8 MPU regions are implemented. All other values Reserved Reserved Reserved. Reads return 0. System Memory Protection Unit (NMPU) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 479: Mpu Region Base Address Register (Mpuregbase)
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset Table 11-14. MPU Region Size and Enable Register (MPUREGSENA) Field Descriptions Field Value Description 31-6 Reserved Reserved. Reads return 0. SPNU563A – March 2018 System Memory Protection Unit (NMPU) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 480 MPU Region Enable. This is the register bit for enabling an MPU region. Read: MPU region is disabled. MPU region is enabled. Write in Privilege: Disable MPU region. Enable MPU region. System Memory Protection Unit (NMPU) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 481: Mpu Region Access Control Register (Mpuregacr)
Read/write. No access. Read only in privileged mode; No access in user mode. Read only. No access. Reserved Reserved. Reads return 0. SPNU563A – March 2018 System Memory Protection Unit (NMPU) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 482: Mpu Region Number Register (Mpuregnum)
Access MPU region 3 registers. Access MPU region 4 registers. Access MPU region 5 registers. Access MPU region 6 registers. Access MPU region 7 registers. System Memory Protection Unit (NMPU) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 483: Error Profiling Controller (Epc)
This chapter describes overall functionality and how to use the Error Profiling Controller (EPC)..........................Topic Page ......................12.1 Overview ..................... 12.2 Module Operation ....................12.3 How to Use EPC ..................12.4 EPC Control Registers SPNU563A – March 2018 Error Profiling Controller (EPC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 484: Overview
4. If CAM overflow happens, EPC will set CAM overflow status bit (cam ovflw) in EPCERRSTAT register. 5. You can access CAM content and CAM index during functional and diagnostic run time. Error Profiling Controller (EPC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 485: Uncorrectable Fault Operation
IP memory during diagnostic time. You can write clears the corresponding FIFO full or overflow status bit in privilege mode. SPNU563A – March 2018 Error Profiling Controller (EPC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 486 ESM. This is done to test the signal chain in CAM content update for unique address and triggering correctable event in functional mode. Error Profiling Controller (EPC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 487: How To Use Epc
SPNU563A – March 2018 Error Profiling Controller (EPC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 488: Cam Diagnostic Mode
CAM_INDEX5 CAM Index Register 5 Section 12.4.10 218h CAM_INDEX6 CAM Index Register 6 Section 12.4.10 21Ch CAM_INDEX7 CAM Index Register 7 Section 12.4.10 Error Profiling Controller (EPC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 489: Epc Revid Register (Epcrevid)
A0Ah Indicates functionally equivalent module family. 15-11 RTL version number. 10-8 MAJOR Major revision number. CUSTOM Indicates device-specific implementation. MINOR Minor revision number. SPNU563A – March 2018 Error Profiling Controller (EPC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 490: Epc Control Register (Epccntrl)
All other values Reserved Write in Privilege: serr_event generation is disabled. serr_event generation is enabled. All other values Reserved Error Profiling Controller (EPC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 491: Uncorrectable Error Status Register (Uerrstat)
Uncorrectable ECC fault status bit is not active for interface n. Uncorrectable ECC fault status bit is active for interface n. Write in Privilege: No effect. Clear this flag bit. SPNU563A – March 2018 Error Profiling Controller (EPC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 492: Epc Error Status Register (Epcerrstat)
CAM overflow status bit. CAM is full and there is another correctable address arrives. Read: No CAM overflow. CAM overflow is detected. Write in Privilege: No effect. Clear this flag bit. Error Profiling Controller (EPC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 493: Fifo Full Status Register (Fifofullstat)
Unimplemented bits are reserved and are not writable. Reserved bits are read as 0. Read: FIFO interface n is not full. FIFO interface n full occurred. Write in Privilege: No effect. Clear this flag bit. SPNU563A – March 2018 Error Profiling Controller (EPC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 494: Ip Interface Fifo Overflow Status Register (Ovrflwstat)
Number of current available CAM index. These bits indicate (binary encoded value) the number of currently available CAM index. Reserved 1 CAM index is available. 2 CAM index is available. 32 CAM index is available. Error Profiling Controller (EPC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 495: Uncorrectable Error Address Register N (Uerr_Addr)
11Ch corresponds to index 31. The number of active registers changes depending on the number of CAM indexes available upon configuration during device integration. Reserved Reserved. Reads return 0. SPNU563A – March 2018 Error Profiling Controller (EPC) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 496: Cam Index Registers (Cam_Index[0-7])
CAM Index Register 6 index 27 index 26 index 25 index 24 21Ch CAM Index Register 7 index 31 index 30 index 29 index 28 Error Profiling Controller (EPC) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 497: Cpu Compare Module For Cortex-R5F (Ccm-R5F)
........................... Topic Page ......................13.1 Overview ..................... 13.2 Module Operation ..................... 13.3 Control Registers SPNU563A – March 2018 CPU Compare Module for Cortex-R5F (CCM-R5F) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 498: Overview
CCM-R5F. The same approach is used for the key power domains if inactive signals indicate that bus masters inside these power domains are asserting valid bus transactions. CPU Compare Module for Cortex-R5F (CCM-R5F) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 499: Module Operation
CPU output compare as described above as well as to the VIM output compare. SPNU563A – March 2018 CPU Compare Module for Cortex-R5F (CCM-R5F) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 500: Cpu/Vim Output Compare Diagnostic
CPU Compare Module for Cortex-R5F (CCM-R5F) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 501 Compare Match Test. Table 13-1. Compare Match Test Sequence CPU 1 (Main CPU) Signal Position CPU 2 (Checker CPU) Signal Position Cycle SPNU563A – March 2018 CPU Compare Module for Cortex-R5F (CCM-R5F) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 502 Table 13-2. CPU / VIM Compare Mismatch Test Sequence CPU 1 (Main CPU) Signal Position CPU 2 (Checker CPU) Signal Position Cycle n–1:8 n–1:8 –1 2n-1 CPU Compare Module for Cortex-R5F (CCM-R5F) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 503 Enabled Enabled Error Forcing 1001 Error Error Disabled Disabled Disabled Disabled Self-Test 1111 Error Enabled Enabled Disabled Disabled Disabled Error Forcing SPNU563A – March 2018 CPU Compare Module for Cortex-R5F (CCM-R5F) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 504: Cpu Input Inversion Diagnostic
Indicates write address and control are valid ARVALIDP Indicates write address and control are valid HTRANSP[1:0] Indicates write address and control are valid CPU Compare Module for Cortex-R5F (CCM-R5F) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 505: Checker Cpu Inactivity Monitor
Compare Match Test ii. Compare Mismatch Test CCM-R5F first generates Compare Match Test patterns, followed by Compare Mismatch Test patterns. SPNU563A – March 2018 CPU Compare Module for Cortex-R5F (CCM-R5F) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 506 ESM error flag “CCM-R5F - self-test” is expected after the self-test error forcing mode completes. Once the expected errors are seen, the application can clean the error through the ESM module. CPU Compare Module for Cortex-R5F (CCM-R5F) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 507: Power Domain Inactivity Monitor
CCM-R5F Status Register 4 Section 13.3.8 CCMKEYR4 CCM-R5F Key Register 4 Section 13.3.9 CCMPDSTAT0 CCM-R5F Power Domain Status Register 0 Section 13.3.10 SPNU563A – March 2018 CPU Compare Module for Cortex-R5F (CCM-R5F) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 508: Ccm-R5F Status Register 1 (Ccmsr1)
Read/Write in User and Privileged mode. Read: Self-test passed. Write: Writes have no effect. Read: Self-test failed. Write: Writes have no effect. CPU Compare Module for Cortex-R5F (CCM-R5F) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 509: Ccm-R5F Key Register 1 (Ccmkeyr1)
Note: It is recommended to not write any other key combinations. Invalid keys will result in switching operation to lockstep mode. SPNU563A – March 2018 CPU Compare Module for Cortex-R5F (CCM-R5F) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 510: Ccm-R5F Status Register 2 (Ccmsr2)
Read/Write in User and Privileged mode. Read: Self-test passed. Write: Writes have no effect. Read: Self-test failed. Write: Writes have no effect. CPU Compare Module for Cortex-R5F (CCM-R5F) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 511: Ccm-R5F Key Register 2 (Ccmkeyr2)
Note: It is recommended to not write any other key combinations. Invalid keys will result in switching operation to lockstep mode. SPNU563A – March 2018 CPU Compare Module for Cortex-R5F (CCM-R5F) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 512: Ccm-R5F Status Register 3 (Ccmsr3)
Read/Write in User and Privileged mode. Read: Self-test passed. Write: Writes have no effect. Read: Self-test failed. Write: Writes have no effect. CPU Compare Module for Cortex-R5F (CCM-R5F) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 513: Ccm-R5F Key Register 3 (Ccmkeyr3)
CPU1 to the CCM-R5F. Inverting any one signal will lead to compare error by the CPU Output Compare Diagnostic. Read in User and Privileged mode. Write in Privileged mode only. SPNU563A – March 2018 CPU Compare Module for Cortex-R5F (CCM-R5F) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 514: Ccm-R5F Status Register 4 (Ccmsr4)
Read/Write in User and Privileged mode. Read: Self-test passed. Write: Writes have no effect. Read: Self-test failed. Write: Writes have no effect. CPU Compare Module for Cortex-R5F (CCM-R5F) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 515: Ccm-R5F Key Register 4 (Ccmkeyr4)
Note: It is recommended to not write any other key combinations. Invalid keys will result in switching operation to lockstep mode. SPNU563A – March 2018 CPU Compare Module for Cortex-R5F (CCM-R5F) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 516: Ccm-R5F Power Domain Status Register 0 (Ccmpdstat0)
Write: Writes have no effect. Any non-zero Read: An unexpected bus transaction is detected on the master. value Write: Writes have no effect. CPU Compare Module for Cortex-R5F (CCM-R5F) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 517: Oscillator And Pll
Low Power Oscillator and Clock Detect (LPOCLKDET) ......................... 14.5 ..................14.6 PLL Control Registers ............14.7 Phase-Locked Loop Theory of Operation ..................14.8 Programming Example SPNU563A – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 518: Introduction
– Configurable modulation depth (NV) • The slip control circuitry provides flexible response to a PLL failure (slip) including reset or automatic switch over to oscillator. Oscillator and PLL SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 519: Quick Start
Figure 14-1. Clock Path from Oscillator through PLL to Device load capacitor device pin CLKDET PLL1 slip PLL2 Clock source numbering can be found in the device data sheet. crystal device pin KELVIN_GND SPNU563A – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 520: Oscillator
The crystal is a very tight bandpass filter while a resonator is a somewhat wider bandpass. The load circuitry pulls the center frequency of the bandpass. Texas Instruments strongly encourages each customer to submit samples of the device to the resonator/crystal vendor for validation. The vendor is equipped to determine what load capacitances will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature and voltage extremes.
Page 521: Oscillator Implementation
The oscillator disable signal places the oscillator into a low-power state, disconnects the feedback (bias) resistor between OSCIN and OSCOUT, and OSCIN is grounded. SPNU563A – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 522: Low Power Oscillator And Clock Detect (Lpoclkdet)
• GCM clock source 0 (replacing the oscillator) • GCM clock source 1 (replacing the PLL) • GCM clock source 5 as HF LPO Oscillator and PLL SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 523: Recovery From Oscillator Failure
(overriding the oscillator invalid signal) after 16K LF LPO cycles (about 200 ms). SPNU563A – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 524: Lpoclkdet Disable
HFTRIM setting from the OTP, the crystal oscillator may be used as a reference against which the HF LPO and LF LPO may be further adjusted. Oscillator and PLL SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 525: Pll
Table 14-1. Valid Frequency Ranges for PLL Frequency Limit CLKIN (OSC_Sqr) 1MHz - f INTCLK (OSC_Sqr) 150MHz - 550MHz Output CLK post-ODCLK (post_ODCLK) PLL CLK (GCLK) SPNU563A – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 526 VCLK, then the gating produces a short-term change in the PLL clock frequency (and hence also the VCLK frequency). As such, this frequency change could violate the requirements for an asynchronous clock domain. Oscillator and PLL SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 527: Modulation
A M O U N T S P R R AT E (11) NOTE: Modulation should be enabled after Lock Enable modulation after the lock is completed. SPNU563A – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 528: Pll Output Control
CLKSRnV bit for the PLL is set in the Clock Source Valid Status Register (CSVSTAT) of the System and Peripheral Control Registers. Oscillator and PLL SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 529 Typically, any change to the REFCLKDIV field or large changes to the PLLMUL field in the PLL Control Register 1 (PLLCTL1) of the System and Peripheral Control Registers requires a complete disable-and-relock strategy. SPNU563A – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 530 = 6 x T Enable OSCIN Disable clocks after lock = 150 x T Enable OSCIN Change ODPLL = 3 x T ODPLL OSCIN Oscillator and PLL SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 531: Behavior On Pll Fail
PLL Bypass CLK Clock Control Module PLL CLK Input from FMzPLL Oscillator Bypass on Slip BPOS Slip Detector To Device Reset BPOS Reset on Slip SPNU563A – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 532: Recovery From A Pll Failure
4. Re-enable PLL2 by setting the appropriate bit in the Clock Source Disable Clear Register (CSDISCLR). 5. Switch the clock domains back to PLL2. Oscillator and PLL SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 533: Pll Modulation Depth Measurement
Any PLL error can be handled by the CPU. PLL2 is programmed through PLLCTL3. SPNU563A – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 534: Pll Control Registers
Table 14-5. LPOCLKDET Module Registers Address Acronym Register Description Section FFFF FF88h LPOMONCTL LPO/CLock Monitor Control Register Section 2.5.1.31 FFFF FF8Ch CLKTEST Clock Test Register Section 2.5.1.31 Oscillator and PLL SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 535: Pll Modulation Depth Measurement Control Register (Sswpll1)
If EXT_COUNTER_EN = 0, COUNTER_EN = 1 indicates that the counters are still active. If EXT_COUNTER_EN = 1, COUNTER_EN = 1 enables the counters. SPNU563A – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 536: Ssw Pll Bist Control Register 2 (Sswpll2)
Capture count. This register returns the value of the capture count. When EXT_COUNTER_EN = 0, this counter increments within a fixed modulation window. When EXT_COUNTER_EN = 1, this counter increments based upon the oscillator. Oscillator and PLL SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 537: Ssw Pll Bist Control Register 3 (Sswpll3)
Table 14-8. SSW PLL BIST Control Register 3 (SSWPLL3) Field Descriptions Field Description 31-0 SSW_CAPTURE_COUNT Value of CLKout count register. This counter increments based upon the PLL output (prior to the R-divider). SPNU563A – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 538: Phase-Locked Loop Theory Of Operation
Figure 14-10. PFD Timing Input reference Feedback divider output Leading phase Lagging phase Down Interpulse slope caused by filter time constant and leakage VCO control voltage Oscillator and PLL SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 539: Charge Pump And Loop Filter
Figure 14-11. PLL Modulation Block Diagram post-ODCLK Output CLK INTCLK PLL CLK CLKIN ÷ ÷ ÷ ÷ Feedback ÷ Divider SPNU563A – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 540: Frequency Modulation
4. Select the output divider OD so that the post-ODCLK frequency does not exceed the maximum frequency of output divider R (device-specific frequency). In this case, choose OD = 2 and R = 1. Oscillator and PLL SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 541 The Output CLK is centered in the range from 150 MHz to 550 MHz at 360 MHz. NF = 90 falls within the multiplier range from 1 to 256. OD is selected so that post-ODCLK meets the device specification. SPNU563A – March 2018 Oscillator and PLL Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 542: Dual-Clock Comparator (Dcc) Module
Topic Page ..................... 15.1 Introduction ..................... 15.2 Module Operation ..........15.3 Clock Source Selection for Counter0 and Counter1 ..................15.4 DCC Control Registers Dual-Clock Comparator (DCC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 543: Introduction
Error (to ESM) Compare and Control Logic Done (to VIM) Preload Count 1 Reload Reload Single Sequence Clock 1 Mode Down Counter 1 SPNU563A – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 544: Module Operation
• The module is reset or restarted by the application, OR • Counter0, Valid 0 and Counter1 all reach 0 without any error Dual-Clock Comparator (DCC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 545 Figure 15-3. Clock1 Slower Than Clock0 - Results in an Error and Stops Counting Error Count0 Clock0 Valid0 Count1 Clock1 time reload Counter1 does not reach 0 before VALID0 reaches 0 SPNU563A – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 546 1 time reload An error signal is generated since Count1 does not reach 0 in the Valid0 window. Dual-Clock Comparator (DCC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 547: Single-Shot Measurement Mode
ESM whenever this DCC error is indicated. Refer the device datasheet to identify the ESM group and channel where the DCC error is connected. SPNU563A – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 548: Clock Source Selection For Counter0 And Counter1
The selection of the clock sources for counter0 and coutner1 is done by a combination of the KEY, CNT0 CLKSRC, and CNT1 CLKSRC control fields of the CNT0CLKSRC and CNT1CLKSRC registers. Dual-Clock Comparator (DCC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 549: Dcc Control Registers
DCC Counter1 Value Register Section 15.4.9 DCCCNT1CLKSRC DCC Counter1 Clock Source Selection Register Section 15.4.10 DCCCNT0CLKSRC DCC Counter0 Clock Source Selection Register Section 15.4.11 SPNU563A – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 550: Dcc Global Control Register (Dccgctrl)
Write: Load counters with their seed values and begin counting. It is recommended to write Ah to enable counters to protect against single-bit errors. Dual-Clock Comparator (DCC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 551: Dcc Revision Id Register (Dccrev)
NOTE: Seed for Counter0 must be non-zero The DCC must only be enabled after programming a non-zero value in the COUNT0 SEED register. SPNU563A – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 552: Dcc Valid0 Seed Register (Dccvalid0Seed)
NOTE: Seed for Counter0 must be non-zero The DCC must only be enabled after programming a non-zero value in the COUNT1 SEED register. Dual-Clock Comparator (DCC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 553: Dcc Status Register (Dccstat)
Read: DCC error has not occurred. Write: Writing 0 has no effect. Read: An error has occurred. Write: Writing 1 in privileged mode clears the ERR flag. SPNU563A – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 554: Dcc Counter0 Value Register (Dcccnt0)
NOTE: Reads may not return exact current value of counter Reading the counter0 value while counting is enabled may not return the exact value of the counter0. Dual-Clock Comparator (DCC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 555: Dcc Valid0 Value Register (Dccvalid0)
NOTE: Reads may not return exact current value of counter Reading the counter1 value while counting is enabled may not return the exact value of the counter1. SPNU563A – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 556: Dcc Counter1 Clock Source Selection Register (Dcccnt1Clksrc)
Writes in privileged mode select the clock source for counter1. Refer to the device datasheet for available clock source options and the KEY required to enable these options for counter1. Dual-Clock Comparator (DCC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 557: Dcc Counter0 Clock Source Selection Register (Dcccnt0Clksrc)
Reads in any operating mode return the current value of CLKSRC. Writes in privileged mode select the clock source for counter0. Refer to the device datasheet for available clock source options for counter0. SPNU563A – March 2018 Dual-Clock Comparator (DCC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 558: Error Signaling Module (Esm)
........................... Topic Page ......................16.1 Overview ..................... 16.2 Module Operation ............. 16.3 Recommended Programming Procedure ..................16.4 ESM Control Registers Error Signaling Module (ESM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 559: Overview
Handling Note that the ESM Status Register 1 (ESMSR1) for error_group1 gets updated, regardless if the interrupt enable is active or not. SPNU563A – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 560 Controlled by: ESMIEPSR1 Low-Time ESMIEPCR1 Counter Preload ESMIEPSR4 Error Signal (LTCP ESMIEPCR4 Control ESMIEPSR7 ESMIEPCR7 Low-Time Device error_group2 Counter Output ERROR (LTC) error_group3 ESMEPSR Error Signaling Module (ESM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 561: Module Operation
ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the ESMSR1, ESMSR4, ESMSR7 and the shadow register ESMSSR2. Reading ESMIOFFLR will also not clear the ESMSR1, ESMSR4 and ESMSR7. SPNU563A – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 562: Error Pin Timing
In this case, the ERROR pin is set to high immediately after ERROR pin ERROR_low reset request is received. Figure 16-6. ERROR Pin Timing - Example 3 failure ERROR pin reset request ERROR ERROR_low Error Signaling Module (ESM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 563: Forcing An Error Condition
Figure 16-9. ERROR Pin Timing - Example 6 failure Write “0101” to ESMEKR Write “1010” to ESMEKR Write “0” to ESMEKR ERROR ERROR_low SPNU563A – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 564: Recommended Programming Procedure
ESMIEPSR7, ESMIEPCR7, ESMIESR7, and ESMIECR7). Define ESM Low-Time Counter Preload Register ESMLTCPR to determine the ERROR low time in case an error occurs. Error Signaling Module (ESM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 565: Esm Control Registers
ESMILSR7 Interrupt Level Set/Status Register 7 Section 16.4.28 ESMILCR7 Interrupt Level Clear/Status Register 7 Section 16.4.29 ESMSR7 ESM Status Register 7 Section 16.4.30 SPNU563A – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 566: Esm Enable Error Pin Action/Response Register 1 (Esmeepapr1)
Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR1 register. Error Signaling Module (ESM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 567: Esm Interrupt Enable Set/Status Register 1 (Esmiesr1)
Write: Leaves the bit and the corresponding set bit in the ESMIESR1 register unchanged. Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR1 register. SPNU563A – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 568: Esm Interrupt Level Set/Status Register 1 (Esmilsr1)
Read: Interrupt of channel x is mapped to high-level interrupt line. Write: Maps interrupt of channel x to low-level interrupt line and clears the corresponding set bit in the ESMILSR1 register. Error Signaling Module (ESM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 569: Esm Status Register 1 (Esmsr1)
Note: In normal operation the flag gets cleared when reading the appropriate vector in the ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the ESMSR1 and the shadow register ESMSSR2. SPNU563A – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 570: Esm Status Register 3 (Esmsr3)
Note: This flag will be set to 1 after PORRST. The value will be unchanged after RST. The ERROR pin status remains unchanged during after RST. Error Signaling Module (ESM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 571: Esm Interrupt Offset High Register (Esmioffhr)
Note: Reading the interrupt vector will clear the corresponding flag in the ESMSR2 register; will not clear ESMSR1 and ESMSSR2 and the offset register gets updated. User and privileged mode (write): Writes have no effect. SPNU563A – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 572: Esm Interrupt Offset Low Register (Esmiofflr)
Note: Reading the interrupt vector will not clear the corresponding flag in the ESMSR1 register. Group2 interrupts are fixed to the high level interrupt line only. User and privileged mode (write): Writes have no effect. Error Signaling Module (ESM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 573: Esm Low-Time Counter Register (Esmltcr)
ERROR Pin Low-Time Counter Pre-load Value 16-bit pre-load value for the ERROR pin low-time counter. Note: Only LTCP.15 and LTCP.14 are configurable (privileged mode write). SPNU563A – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 574: Esm Error Key Register (Esmekr)
Write: Clears the bit. ESMSR2 is not impacted by this action. Note: Errors are stored until they are cleared by the software or at power-on reset (PORRST). Error Signaling Module (ESM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 575: Esm Influence Error Pin Set/Status Register 4 (Esmiepsr4)
Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding clear bit in the ESMIEPSR4 register. SPNU563A – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 576: Esm Interrupt Enable Set/Status Register 4 (Esmiesr4)
Write: Leaves the bit and the corresponding clear bit in the ESMIESR4 register unchanged. Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding clear bit in the ESMIESR4 register. Error Signaling Module (ESM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 577: Esm Interrupt Level Set/Status Register 4 (Esmilsr4)
Read: Interrupt of channel x is mapped to high-level interrupt line. Write: Maps interrupt of channel x to low-level interrupt line and clears the corresponding set bit in the ESMILSR4 register. SPNU563A – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 578: Esm Status Register 4 (Esmsr4)
Note: After RST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called. Error Signaling Module (ESM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 579: Esm Influence Error Pin Set/Status Register 7 (Esmiepsr7)
Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding clear bit in the ESMIEPSR7 register. SPNU563A – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 580: Esm Interrupt Enable Set/Status Register 7 (Esmiesr7)
Write: Leaves the bit and the corresponding clear bit in the ESMIESR7 register unchanged. Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding clear bit in the ESMIESR7 register. Error Signaling Module (ESM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 581: Esm Interrupt Level Set/Status Register 7 (Esmilsr7)
Read: Interrupt of channel x is mapped to high-level interrupt line. Write: Maps interrupt of channel x to low-level interrupt line and clears the corresponding set bit in the ESMILSR7 register. SPNU563A – March 2018 Error Signaling Module (ESM) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 582: Esm Status Register 7 (Esmsr7)
Note: After RST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called. Error Signaling Module (ESM) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 583: Real-Time Interrupt (Rti) Module
........................... Topic Page ......................17.1 Overview ..................... 17.2 Module Operation ..................17.3 RTI Control Registers SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 584: Overview
Schnittstellen für die Elektronik im Kraftfahrzeug, or Open Systems and the Corresponding Interfaces for Automotive Electronics) as well as OSEK/time-compliant operating systems, but is not limited to it. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 585: Module Operation
The counter values can be determined by reading the respective counter registers or by generating a hardware event which captures the counter value into the respective capture register. Both functions are described in the following sections. SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 586 To Compare Free Running Counter RTICLK Up Counter Unit RTIFRC1 Up Counter Register RTIUC1 Capture Up Capture Free Running Counter Counter RTICAUC1 RTICAFRC1 Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 587: Interrupt/Dma Requests
RTICLK if RTICPUCy ≠ (2 +1) x RTIUDCPy COMPx RTICLK if RTIUDCPy = 0, x (RTICPUCy + 1) x 2 (24) COMPx RTICLK SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 588: Rti Clocking
RTIUC0 happens, RTICPUC0 should be set to a value so the clock frequency RTIUC0 outputs is approximately the same as the NTUx frequency. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 589 NOTE: To ensure the NTUx signal is properly detected, the NTUx period must be at least twice as long as the RTICLK period. Figure 17-5. Clock Detection Scheme RTIUC0 RTICPUC0 RTITBLCOMP RTITBHCOMP Active Edge time Detection NTUx SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 590 NTU pulse. Setting TBEXT = 0 will also switch the clock source for RTIFRC0 to RTIUC0. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 591: Digital Watchdog (Dwd)
KEY [1:0] 16 bit out to 2 DWD down counter RTICLK RTIDWDCNTR Suspend nTRST DWD preload DWD ctrl DWD hardwired RTIDWDPRLD RTIDWDCTRL code SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 592 DWWD is configured to generate a non-maskable interrupt on a window violation, the watchdog counter continues to count down. The NMI handler needs to clear the watchdog violation status flag(s) and then Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 593 Value left shifted 11bits DWD can NOT be served in this period time Reset/NMI Config Write enable set DWD access Preload Keys to DWD Window SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 594: Low Power Modes
NTU signal of the suspended communication controller. This will be signaled with an TBINT interrupt so that software can resynchronize after the device exits halting debug mode. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 595: Rti Control Registers
RTI Compare 1 Clear Register Section 17.3.37 RTICOMP2CLR RTI Compare 2 Clear Register Section 17.3.38 RTICOMP3CLR RTI Compare 3 Clear Register Section 17.3.39 SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 596: Rti Global Control Register (Rtigctrl)
COS setting in the RTI module and the halting debug mode behavior of the communications controller. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 597 When the timebase supervisor circuit detects a missing clock edge, then the TBEXT bit is reset. Only the software can select whether the external signal should be used. RTIUC0 clocks RTIFRC0. NTU clocks RTIFRC0. SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 598 RTIUC0 and RTIFRC0. Capture of RTIUC0/ RTIFRC0 is triggered by capture event source 0. Capture of RTIUC0/ RTIFRC0 is triggered by capture event source 1. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 599 Compare select 0. This bit determines the counter with which the compare value held in compare register 0 (RTICOMP0) is compared. Value will be compared with RTIFRC0. Value will be compared with RTIFRC1. SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 600 Note: If the preset value is bigger than the compare value stored in register RTICPUC0, then it can take a long time until a compare matches, since RTIUC0 has to count up until it overflows. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 601 0 (RTIFRC0) when an event occurs, controlled by the external capture control block. A read of this register returns the value of RTIFRC0 on a capture event. SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 602 A write to this register presets the counter. The counter increments then from this written value upwards. Note: If counters must be preset, they must be disabled in the RTIGCTRL register to ensure consistency between RTIUC1 and RTIFRC1. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 603 Note: If the preset value is bigger than the compare value stored in register RTICPUC1, then it can take a long time until a compare matches, since RTIUC1 has to count up until it overflows. SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 604 If CPUC1 ≠ 0, then = RTICLK/(RTICPUC1+1) FRC1 A read of this register returns the current compare value. A write to this register updates the compare value. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 605 RTICAFRC1 register, even if another capture event happens in between the two reads. A read of this register returns the value of RTIUC1 on a capture event. SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 606 A read of this register will return the value to be added to the RTICOMP0 register on the next compare match. A write to this register will provide a new update value. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 607 A read of this register will return the value to be added to the RTICOMP1 register on the next compare match. A write to this register will provide a new update value. SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 608 A read of this register will return the value to be added to the RTICOMP2 register on the next compare match. A write to this register will provide a new update value. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 609 A read of this register will return the value to be added to the RTICOMP3 register on the next compare match. A write to this register will provide a new update value. SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 610 A write to this register has the following effects: If TBEXT = 0: The compare value is updated. If TBEXT = 1: The compare value is not changed. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 611 SETDMA1 Set compare DMA request 1. Read: DMA request is disabled. Write: DMA request is unchanged. Read or Write: DMA request is enabled. SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 612 Read or Write: Interrupt is enabled. SETINT0 Set compare interrupt 0. Read: Interrupt is disabled. Write: Corresponding bit is unchanged. Read or Write: Interrupt is enabled. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 613 Clear compare DMA request 2. Read: DMA request is disabled. Write: Corresponding bit is unchanged. Read: DMA request is enabled. Write: DMA request is disabled. SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 614 Write: Interrupt is disabled. CLEARINT0 Clear compare interrupt 0. Read: Interrupt is disabled. Write: Corresponding bit is unchanged. Read: Interrupt is enabled. Write: Interrupt is disabled. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 615 Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending. Read: No interrupt is pending. Write: Bit is unchanged. Read: Interrupt is pending. Write: Bit is cleared to 0. SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 616 DWD is enabled, it can only be disabled by system reset or power on reset. However should the RTICLK source be changed to a source that is unimplemented it will have the same effect as disabling the watchdog. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 617 The expiration time of the DWD Down Counter can be determined with following equation: texp = (DWDPRLD+1) x 2 / RTICLK1 where: DWDPRLD = 0...4095 SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 618 Write: Bit is unchanged. Read: Reset or NMI was generated. Write: Bit is cleared to 0. Reserved Reads return 0. Writes have no effect. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 619 Watchdog is reset. E51Ah WDKEY is enabled for reset or NMI by next A35Ch. 2345h System reset or NMI; incorrect value written to WDKEY. SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 620 WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 621 WWDSIZE is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced. SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 622 Privileged Write: Auto-clear for compare 0 interrupt becomes disabled. All other values Read: Auto-clear for compare 0 interrupt is enabled. Privileged Write: Auto-clear for compare 0 interrupt becomes enabled. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 623 Reads return the current compare clear value. A privileged write to this register updates the compare clear value. SPNU563A – March 2018 Real-Time Interrupt (RTI) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 624 Reads return the current compare clear value. A privileged write to this register updates the compare clear value. Real-Time Interrupt (RTI) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 625 ........................... Topic Page ......................18.1 Overview ..................... 18.2 Module Operation ......................18.3 Example ..................18.4 CRC Control Registers SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 626 Generate DMA request per channel to initiate CRC value transfer. 18.1.2 Block Diagram Figure 18-1 shows a block diagram of the CRC controller. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 627 Time Logic Preload CRC Timeout Interrupt Register Counter CH2_INT CRC_INT CH3_INT CH4_INT 16 Bit 16 Bit Sector Sector Count Counter Preload SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 628 PSA Signature Register and compare the calculated signature to the pre-determined CRC signature value. In Full-CPU mode, neither interrupt nor DMA request is generated. All counters are also disabled. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 629 CPU itself can also perform data transfer by reading from the memory system and perform write operation to PSA Signature Register if CPU has enough throughput to handle data patterns transfer. SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 630 The PSA Signature Register can be updated with new signature before the host CPU is able to retrieve it. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 631 CRC_SCOUNT_REGx of the respective channel. CRC_PCOUNT_REGx multiplies CRC_SCOUNT_REGx and multiplies transfer size of each data pattern should give the total block size in number of bytes. SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 632 Sector 1 CRC value Sector 2 CRC value PSA Sig Reg CRC Value Reg DMA channel 15 Sector n CRC value Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 633 CRC failure, it is advisable to use the following equation during CRC and DMA setup: CRC Pattern Count × CRC Sector Count = DMA Element Count × DMA Frame Count SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 634 PSA Sector Signature Register. If the host CPU does not read the signature from PSA Sector Signature Register before it is updated again with a new signature value then an overrun interrupt is generated. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 635 Note: No timeout interrupt is generated in this example since each block of data patterns are compressed in 3 ms and DMA does initiate a block transfer every 10 ms. SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 636 DMA is set up in fixed priority scheme and DMA is serving other higher priority channels at the time before it can service the timer request. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 637: Power Down Mode
Timeout counters are stopped to generate timeout interrupts in emulation mode. No Peripheral Master bus error should be generated if reading from the unimplemented locations. SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 638: Peripheral Bus Interface
Set up timer to generate DMA request associated with DMA channel 2. For example, an OS can set up the timer to generate a DMA request every 10ms. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 639: Example: Auto Mode Without Using Time Based Triggering
CPU. Responding to the DMA interrupt CPU can restart the CRC routine by generating a software DMA request onto channel 2 again. SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 640: Example: Semi-Cpu Mode
A memory area with 2Mbyte is to be checked with the help of the CPU. CRC verification is to be performed every 1K byte. In CPU mode, the CRC Value Register is not updated and contains indeterminate data. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 641: Crc Control Registers
Channel 2 PSA Sector Signature High Register Section 18.4.32 RAW_DATAREGL2 Channel 2 Raw Data Low Register Section 18.4.33 RAW_DATAREGH2 Channel 2 Raw Data High Register Section 18.4.34 SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 642: Crc Global Control Register 0 (Crc_Ctrl0)
Power Down. When set, CRC module is put in power-down mode. CRC is not in power-down mode. CRC is in power-down mode. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 643: Crc Global Control Register 2 (Crc_Ctrl2)
Register without any compression. This mode can be used to plant seed value into the PSA register. AUTO Mode Semi-CPU Mode Full-CPU Mode SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 644: Crc Interrupt Enable Set Register (Crc_Ints)
User and Privileged mode (read): CRC Fail Interrupt is disabled. CRC Fail Interrupt is enabled. Privileged mode (write): No effect. CRC Fail Interrupt is enabled. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 645 User and Privileged mode (read): Compression Complete Interrupt is disabled. Compression Complete Interrupt is enabled. Privileged mode (write): No effect. Compression Complete Interrupt is enabled. SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 646: Crc Interrupt Enable Reset Register (Crc_Intr)
User and Privileged mode (read): CRC Fail Interrupt disabled. CRC Fail Interrupt is enabled. Privileged mode (write): No effect. CRC Fail Interrupt is disabled. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 647 User and Privileged mode (read): Compression Complete Interrupt is disabled. Compression Complete Interrupt is enabled. Privileged mode (write): No effect. Compression Complete Interrupt is disabled. SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 648: Crc Interrupt Status Register (Crc_Status)
User and Privileged mode (read): No CRC Fail Interrupt is active CRC Fail Interrupt is active Privileged mode (write): No effect Bit is cleared Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 649 User and Privileged mode (read): No Compression Complete Interrupt is active. Compression Complete Interrupt is active. Privileged mode (write): No effect. Bit is cleared. SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 650: Crc Interrupt Offset (Crc_Int_Offset_Reg)
Ch2 Compression Complete Bh-10h Reserved Ch1 Overrun Ch2 Overrun 13h-18h Reserved Ch1 Underrun Ch2 Underrun 1Bh-20h Reserved Ch1 Timeout Ch2 Timeout 23h-FFh Reserved Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 651: Crc Busy Register (Crc_Busy)
Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed. SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 652: Crc Sector Counter Preload Register 1 (Crc_Scount_Reg1)
In Semi-CPU mode, this register is used to indicate the sector number for which the compression complete has last happened. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 653: Crc Channel 1 Watchdog Timeout Preload Register A (Crc_Wdtopld1)
CRC for an entire block needs to complete before a timeout interrupt is generated. SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 654: Channel 1 Psa Signature Low Register (Psa_Sigregl1)
31-0 CRC1 Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 655: Channel 1 Crc Value High Register (Crc_Regh1)
Field Descriptions Field Description 31-0 PSASECSIG1 Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register. SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 656: Channel 1 Raw Data Low Register (Raw_Dataregl1)
Channel 2 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 657: Crc Sector Counter Preload Register 2 (Crc_Scount_Reg2)
In Semi-CPU mode, this register is used to indicate the sector number for which the compression complete has last happened. SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 658: Crc Channel 2 Watchdog Timeout Preload Register A (Crc_Wdtopld2)
CRC for an entire block needs to complete before a timeout interrupt is generated. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 659: Channel 2 Psa Signature Low Register (Psa_Sigregl2)
31-0 CRC2 Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register. SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 660: Channel 2 Crc Value High Register (Crc_Regh2)
Field Descriptions Field Description 31-0 PSASECSIG2 Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register. Cyclic Redundancy Check (CRC) Controller Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 661: Channel 2 Raw Data Low Register (Raw_Dataregl2)
Table 18-38. Channel 2 Raw Data High Register (RAW_DATAREGH2) Field Descriptions Field Description 31-0 RAW_DATA2 Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.. SPNU563A – March 2018 Cyclic Redundancy Check (CRC) Controller Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 662: Vectored Interrupt Manager (Vim) Module
Interrupt Vector Table (VIM RAM) ..................19.6 VIM Wakeup Interrupt ..................19.7 Capture Event Sources ......................19.8 Examples ..................19.9 VIM Control Registers Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 663: Overview
Provides two software dispatch mechanisms for backward compatibility with earlier generation of TI processors. – Index interrupt – Register vectored interrupt • ECC (Error Code Correction) protected vector interrupt table against soft errors. SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 664: Dual Vim For Safety
MMR I/F1 To CPU1 Core1 INT_REQ 2 cyc delay 2 cyc delay To CPU2 2 cyc Core2 delay VIM Interrupt Vector Table 2 Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 665: Device Level Interrupt Management
An interrupt flag bit for each event to signify the event occurrence. • An interrupt enable bit to control whether the event occurrence causes an interrupt request to the VIM. SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 666: Interrupt Handling At The Cpu
A write of 1 to CPSR bit 7 disables the IRQ from CPU. However, a write of 1 to CPSR bit 6 leaves it unchanged. Example 19-2 also shows how to disable the IRQ through CPSR. Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 667: Software Interrupt Handling Options
19.9.10) in the VIM. This is not necessary if any of the three previous methods are used as the interrupt request bit in the VIM will be automatically cleared when the vector is read. SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 668: Interrupt Handling Inside Vim
PROGRAMMABLE INTERRUPT VECTOR TABLE FIQINDEX IRQINDEX Phantom Vector Channel 0 Vector Channel 1 Vector Channel 126 Vector TO CPU VIC Port Register Register IRQVECREG FIQVECREG Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 669: Vim Interrupt Channel Mapping
(REQENASET and REQENACLR). When channel 2 is enabled, the priority is: INT0 INT1 INT2 INT3 Disabling channel 2, the priority becomes: INT0 INT1 INT3 INT2 SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 670 CHAN126 Channel 126 Vector 0xFFF821FC INT_REQ126 NOTE: CHAN0 and CHAN1 are hard wired to INT_REQ0 and INT_REQ1, so they cannot be remapped. Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 671: Vim Input Channel Management
FIQ and IRQ classes) to the CPU. Within the FIQ and IRQ classes of interrupts, the lowest channel has the highest priority interrupt. The channel number is programmable through register CHANMAPx. SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 672: Interrupt Vector Table (Vim Ram)
NOTE: The interrupt vector table only has 128 entries, one phantom vector and 127 interrupt channels. Channel 127 does not have a dedicated vector and shall not be used. Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 673: Vim Ecc Syndrome
2. Each ECC bit is built by generating the parity of the XORed bits of the data word, whereas ECC bit 2 and 3 are even parity and the other bits odd parity. Table 19-1. ECC Syndrome Table SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 674: Interrupt Vector Table Initialization
This write will be blocked ECC bits write Normal RAM locations write without ECC bits This write will be blocked This write is not allowed Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 675 0xFFF82000 Word 0 Word 1 Word 2 Word 3 0xFFF82400 ECC0 Read 0 ECC1 Read 0 Read 0 ECC2 ECC3 Read 0 SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 676: Vim Wakeup Interrupt
INT_REQ1 WAKEUP1 WAKEENA.1 Controlled by: WAKEENASET.1 WAKEENACLR.1 INT_REQ2 WAKE_INT WAKEUP2 WAKEENA.2 Controlled by: WAKEENASET.2 WAKEENACLR.2 INT_REQ127 WAKEUP127 WAKEENA.127 Controlled by: WAKEENASET.127 WAKEENACLR.127 Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 677: Capture Event Sources
; Mask 0-31 bits except bit 24 in Sys ; Ctrl Reg of CORTEX-R4 MCR p15 ,#0 ,R1 ,c1 ,c0 ,#0 ; Enable bit 24 MOV PC, LR SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 678: Examples - Register Vector Interrupt And Index Interrupt Handling
‘PC - 0x1B0’, which is ‘0x18 or 0x1C + 0x08 - 0x1B0 = 0xFFFFFE70 or 0xFFFFFE74’. These are the address of IRQVECREG and FIQVECREG, which store the pending ISR address. Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 679 The difference is that the CPU will not read from the 0x18 location during IRQ interrupt, but will jump directly to the corresponding ISR routine. SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 680: Vim Control Registers
Section 19.9.15 FIQVECREG FIQ Interrupt Vector Register Section 19.9.16 CAPEVT Capture Event Register Section 19.9.17 80h-FCh CHANCTRL VIM Interrupt Control Register Section 19.9.18 Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 681: Interrupt Vector Table Ecc Status Register (Eccstat)
Read: A double-bit error has occurred and the Interrupt Vector Table is bypassed. Write: The UERR bit is cleared and the interrupt vector can be read from the Interrupt Vector Table. SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 682: Interrupt Vector Table Ecc Control Register (Eccctl)
All other values VIM ECC is enabled. Note: To avoid soft error to disable VIM ECC checking, it is recommended to write Ah to enable ECC checking. Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 683: Uncorrectable Error Address Register (Uerraddr)
FBVECADDR. The value provided to the VIC port will also reflect FBVECADDR until the UERR register has been cleared. This register provides the address of the ISR that will restore the integrity of the Interrupt Vector Table. SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 684: Single-Bit Error Address Register (Sberraddr)
The VIM offset registers are read only. They are updated continuously by the VIM. When an interrupt is serviced, the offset vectors show the index for the next highest pending interrupt or 0x0 if no interrupt is pending. Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 685: Irq Index Offset Vector Register (Irqindex)
Table 19-11. When no interrupts are pending, the least-significant byte of FIQINDEX is 0x00. SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 686: Fiq/Irq Program Control Registers (Firqpr[0:3])
FIQ or IRQ. Bit FIRQPRx[127:2] corresponds to request channel[127:2]. Interrupt request is of IRQ type. Interrupt request is of FIQ type. Reserved Read only. Writes have no effect. Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 687: Pending Interrupt Read Location Registers (Intreq[0:3])
Clears the interrupt pending status flag. This write-clear functionality is intended to allow clearing those interrupts which have been signaled to VIM before enabling the interrupt channel, if they are undesired. SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 688: Interrupt Enable Set Registers (Reqenaset[0:3])
Read: Interrupt request channel is disabled. Write: No effect. Read or Write: The interrupt request channel is enabled. Reserved Read only. Writes have no effect. Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 689: Interrupt Enable Clear Registers (Reqenaclr[0:3])
Write: No effect. Read: The interrupt request channel is enabled. Write: The interrupt request channel is disabled. Reserved Read only. Writes have no effect. SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 690: Wake-Up Enable Set Registers (Wakeenaset[0:3])
Bit WAKEENASETx[127:0] corresponds to interrupt request channel[127:0]. Read: Interrupt request channel is disabled. Write: No effect. Read or Write:The interrupt request channel is enabled. Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 691: Wake-Up Enable Clear Registers (Wakeenaclr[0:3])
Read: Wake-up interrupt channel is disabled. Write: No effect. Read: The wake-up interrupt channel is enabled. Write: The wake-up interrupt channel is disabled. SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 692: Irq Interrupt Vector Register (Irqvecreg)
FIQ interrupt vector register. This vector gives the address of the ISR with the highest Section 19.5 pending FIQ request. The CPU reads the address and branches to this location. Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 693: Capture Event Register (Capevt)
Capture event source 0 mapping control. These bits determine which interrupt request maps to the capture event source 0 of the RTI: Interrupt request 0. Interrupt request 1. Interrupt request 127. SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 694: Vim Interrupt Control Registers (Chanctrl[0:31])
Write: The default value of this bit after reset is given in Table 19-23. The channel priority CHANx is set with the interrupt request. Reserved Reads are indeterminate and writes have no effect. Vectored Interrupt Manager (VIM) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 695 Write: The default value of this bit after reset is given in Table 19-23. The channel priority CHANx is set with the interrupt request. SPNU563A – March 2018 Vectored Interrupt Manager (VIM) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 696: Direct Memory Access Controller (Dma) Module
This chapter describes the direct memory access (DMA) controller..........................Topic Page ......................20.1 Overview ..................... 20.2 Module Operation ............... 20.3 Control Registers and Control Packets Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 697: Overview
DMA control packets and is secured by ECC. All the programming / configuration of the DMA controller is done via the Peripheral bus. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 698 Hardware Events Control Regs Control Interrupt Packet Port Arbiter Manager BTC, FTC, BER, Port A Port B LFS, HBC, MPV interrupts Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 699: System Resources Mapping
The FIFO is empty at an arbitration boundary. The DMA will utilize this boundary to re-prioritize channels. Within an arbitration boundary, transfers can never be interrupted. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 700: Memory Space
Frame 3 Frame 4 Element 1 Element 2 Element 3 Element 4 Element 5 Element 6 Element 7 Element 8 DMAREQ Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 701: Addressing Modes
20.3.1.3) is changed, then the channel will stop immediately at an arbitration boundary. When the same channel is triggered again, it will begin with the new control packet information. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 702 Current Transfer Count Working CP1 Current Source Address Current Destination Address 0x8F0 Current Transfer Count Current Destination Address Working CPnn Current Source Address Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 703 The current source address field contains the current working source address during a DMA transaction. The current source address is incremented during post increment addressing mode or indexing mode. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 704 This example can be applied to either source or destination indexing and assumes the following setup. Element Size = 16 bit Element Count = 4 Frame Count = 4 Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 705: Priority Queue
Control Packet 14 Control Packet 15 Triggered Channels The above figure illustrates that by default Lower the channel number, higher the Priority. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 706 For optimal system performance, the high priority channels should be put in fixed arbitration scheme and low priority channels in the rotating priority scheme as illustrated in Figure 20-11. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 707: Data Packing And Unpacking
(for example, SCITD register). User should configure DMA to avoid data unpacking if the Destination is configured as Constant Addressing Mode write to avoid data loss. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 708 Equation 26 is not a multiple of the write element size. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 709 NOTE: Since peripherals are slower, it is advised to use data packing feature with caution for reading data from peripherals. Improper use might delay servicing other pending DMA channels. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 710: Dma Request
MIBADC1 event / MIBSPI5[3] DMAREQ[7] SPI1, SPI2, SPI3, SPI4, SPI5 receive in compatibility mode SPI1, SPI2, SPI3, SPI4, SPI5 transmit in compatibility mode Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 711 / MIBSPI2[15] / MIBSPI4[15] / GIOB[5] / DCAN4 IF1 DMAREQ[45] DCAN4 GIOB / DCAN4 GIOB[6] / DCAN4_IF2 DMAREQ[46] GIOB / DCAN4 GIOB[7] / DCAN4_IF3 DMAREQ[47] SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 712: Auto-Initiation
Group B - Interrupts (FTC, LFS, HBC, and BTC) are not routed out. User software should configure only Group A interrupts. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 713 Frame Transfer Complete Ch0 FTC0AB FTCA Frame Transfer Complete Ch31 FTC31AB This figure is applicable for the HBC, LFS, and BTC interrupt. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 714: Debugging
NOTE: When the DMA is in global low power mode, the clock is stopped and therefore it cannot detect any DMA request. The device must be woken up before a peripheral can generate a DMA request. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 715: Fifo Buffer
1 write Size 64 bit 1 read 8 write 1 read 4 write 1 read 2 write 1 read 1 write SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 716: Channel Chaining
4. Program the request polarity for the channel. 5. Re-enable the DMA channel. 6. Re-enable the peripheral that triggers the DMA event. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 717: Memory Protection
DMA Channel that caused the violation will be stopped and the next available DMA channel will be serviced. Figure 20-17 Illustrates a protection mechanism. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 718: Ecc Checking
All channels will stop servicing at the next arbitration boundary. This action will be taken regardless of the origin of error being a CPU read or a DMA logic read. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 719: Ecc Testing
To allow for ECC calculation during initialization, the ECC functionality has to be enabled as discussed in Section 20.2.16. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 720: Transaction Errors
TER_EN Controls TERECTRL Checkers Control Parity TEROFFSET Response Parity Checkers Response Parity DMA_TER_ERR (to ESM) NOTE: Only PortA supports transaction parity Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 721: Control Registers And Control Packets
BTC Interrupt Enable Set Register Section 20.3.1.35 114h BTCINTENAR BTC Interrupt Enable Reset Register Section 20.3.1.36 11Ch GINTFLAG Global Interrupt Flag Register Section 20.3.1.37 SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 722 1FCh DMAMPR7E DMA Memory Protection Region 7 End Address Register Section 20.3.1.83 228h DMASECCCTRL DMA Single-bit ECC Control Register Section 20.3.1.84 Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 723 Current Source Address Register Section 20.3.2.7 804h CDADDR Current Destination Address Register Section 20.3.2.8 808h CTCOUNT Current Transfer Count Register Section 20.3.2.9 SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 724: Global Configuration Registers
Read and write: The DMA state machine and all control registers are in software reset. Control packets are not reset when DMA software reset is active. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 725 DMA is disabled via DMA_EN bit. Since there are two FIFOs, up to 2 bits can be set in this register at any given time. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 726 Reads return 0. Writes have no effect. 27-16 FUNC A0Dh Indicates module family. 15-11 Reserved Reserved 10-8 MAJOR Major revision number. Reserved Reserved MINOR Minor revision number. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 727 Read: The corresponding channel is disabled for HW triggering. Write: No effect. Read: The corresponding channel is enabled for HW triggering. Write: The corresponding channel is disabled. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 728 Read: The corresponding channel was not triggered by SW. Write: No effect. Read: The corresponding channel was triggered by SW. Write: The corresponding channel is disabled. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 729 Read: The corresponding channel is assigned to the high priority queue. Write: The corresponding channel is assigned to the low priority queue. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 730 Read: The corresponding channel is disabled for interrupt. Write: No effect. Read: The corresponding channel is enabled for interrupt. Write: The corresponding channel is disabled for interrupt. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 731 Channel 3 assignment. This bit field chooses the DMA request assignment for channel 3. DMA request line 0 triggers channel 3. DMA request line 47 triggers channel 3. 30h- Reserved SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 732 Channel 7 assignment. This bit field chooses the DMA request assignment for channel 7. DMA request line 0 triggers channel 7. DMA request line 47 triggers channel 7. 30h- Reserved Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 733 Channel 11 assignment. This bit field chooses the DMA request assignment for channel 11. DMA request line 0 triggers channel 11. DMA request line 47 triggers channel 11. 30h- Reserved SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 734 Channel 15 assignment. This bit field chooses the DMA request assignment for channel 15. DMA request line 0 triggers channel 15. DMA request line 47 triggers channel 15. 30h- Reserved Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 735 Channel 19 assignment. This bit field chooses the DMA request assignment for channel 19. DMA request line 0 triggers channel 19. DMA request line 47 triggers channel 19. 30h- Reserved SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 736 Channel 23 assignment. This bit field chooses the DMA request assignment for channel 23. DMA request line 0 triggers channel 23. DMA request line 47 triggers channel 23. 30h- Reserved Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 737 Channel 27 assignment. This bit field chooses the DMA request assignment for channel 27. DMA request line 0 triggers channel 27. DMA request line 47 triggers channel 27. 30h- Reserved SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 738 Channel 31 assignment. This bit field chooses the DMA request assignment for channel 31. DMA request line 0 triggers channel 31. DMA request line 47 triggers channel 31. 30h- Reserved Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 739 Reads return 0. Writes have no effect. CH7PA 0-7h These bit fields determine to which port channel 7 is assigned. Refer to CH0PA for bit value descriptions. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 740 Reads return 0. Writes have no effect. CH15PA 0-7h These bit fields determine to which port channel 15 is assigned. Refer to CH8PA for bit value descriptions. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 741 Reads return 0. Writes have no effect. CH23PA 0-7h These bit fields determine to which port channel 23 is assigned. Refer to CH16PA for bit value descriptions. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 742 Reads return 0. Writes have no effect. CH31PA 0-7h These bit fields determine to which port channel 31 is assigned. Refer to CH24PA for bit value descriptions. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 743 HBC interrupt of the corresponding channel is routed to Group A. HBC interrupt of the corresponding channel is routed to Group B. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 744 BTC interrupt of the corresponding channel is routed to Group A. BTC interrupt of the corresponding channel is routed to Group B. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 745 Read: Corresponding FTC interrupt of a channel is disabled. Write: No effect. Read: Corresponding FTC interrupt of a channel is enabled. Write: Corresponding FTC interrupt is disabled. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 746 Write: No effect. Read: LFS interrupt of the corresponding channel is enabled. Write: LFS interrupt of the corresponding channel is disabled. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 747 Write: No effect. Read: HBC interrupt of the corresponding channel is enabled. Write: HBC interrupt of the corresponding channel is disabled. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 748 Write: No effect. Read: BTC interrupt of the corresponding channel is enabled. Write: BTC interrupt of the corresponding channel is disabled. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 749 Read: FTC interrupt of the corresponding channel is not pending. Write: No effect. Read: FTC interrupt of the corresponding channel is pending. Write: The flag is cleared. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 750 Read: HBC interrupt of the corresponding channel is not pending. Write: No effect. Read: HBC interrupt of the corresponding channel is pending. Write: The flag is cleared. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 751 Imprecise Error and DMA Write Imprecise Error asserted to the ESM module directly, which are detected at the device level. See the ESM error mapping for the DMA Read/Write Imprecise Error. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 752 No interrupt is pending. Channel 0 is causing the pending interrupt Group A. Channel 31 is causing the pending interrupt Group A. 21h- Reserved Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 753 No interrupt is pending. Channel 0 is causing the pending interrupt Group A. Channel 31 is causing the pending interrupt Group A. 21h- Reserved SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 754 No interrupt is pending. Channel 0 is causing the pending interrupt Group A. Channel 31 is causing the pending interrupt Group A. 21h- Reserved Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 755 No interrupt is pending. Channel 0 is causing the pending interrupt Group A. Channel 31 is causing the pending interrupt Group A. 21h- Reserved SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 756 No interrupt is pending. Channel 0 is causing the pending interrupt Group B. Channel 31 is causing the pending interrupt Group B. 21h- Reserved Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 757 No interrupt is pending. Channel 0 is causing the pending interrupt Group B. Channel 31 is causing the pending interrupt Group B. 21h- Reserved SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 758 No interrupt is pending. Channel 0 is causing the pending interrupt Group B. Channel 31 is causing the pending interrupt Group B. 21h- Reserved Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 759 No interrupt is pending. Channel 0 is causing the pending interrupt Group B. Channel 31 is causing the pending interrupt Group B. 21h- Reserved SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 760 Priority scheme fix or rotate for low priority queue. The fixed priority scheme is used. The rotation priority scheme is used. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 761 Note: This bit should be cleared to 0 during normal operation. RAM Test Control is disabled. RAM Test Control is enabled. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 762 Note: This bit is reset when Test reset (TRST) is low. Debug is disabled. The watch point checking logics is enabled. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 763 Allows the bit in the WPR register to be used for address matching for a watch point. Masks the corresponding bit in the WPR register and is disregarded in the comparison. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 764 FIFO A active channel element count. These bits contain the current element count value of the active channel as broadcasted in Section 20.3.1.3 for FIFO A. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 765 FIFO B active channel element count. These bits contain the current element count value of the active channel as broadcasted in Section 20.3.1.3 for FIFO B. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 766 Note: It is recommended to write Ah to enable ECC check, to guard against soft error from flipping ECC_ENA to a disable state. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 767 SUSPEND is high, this address is frozen even when read. Note: The error address register will not be reset by PORRST nor by any other reset source. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 768 Region 2 enable. The region is disabled (no address checking done). The region is enabled (address and access permission checking done). Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 769 Region 0 enable. The region is disabled (no address checking done). The region is enabled (address and access permission checking done). SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 770 Region 0 fault. This bit determines whether a access permission violation was detected in this region. Read: No fault was detected. Write: No effect. Read: A fault was detected. Write: The bit was cleared. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 771 Note: When using 64-bit transfers, the address is rounded up to the nearest 64-bit word end address, that is, 0x200 = 0x207. All other transfers are rounded up to the nearest 32-bit word end address. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 772 Note: When using 64-bit transfers, the address is rounded up to the nearest 64-bit word end address, that is, 0x200 = 0x207. All other transfers are rounded up to the nearest 32-bit word end address. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 773 Note: When using 64-bit transfers, the address is rounded up to the nearest 64-bit word end address, that is, 0x200 = 0x207. All other transfers are rounded up to the nearest 32-bit word end address. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 774 Note: When using 64-bit transfers, the address is rounded up to the nearest 64-bit word end address, that is, 0x200 = 0x207. All other transfers are rounded up to the nearest 32-bit word end address. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 775 Region 6 enable. The region is disabled (no address checking done). The region is enabled (address and access permission checking done). SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 776 Region 4 enable. The region is disabled (no address checking done). The region is enabled (address and access permission checking done). Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 777 Region 4 fault. This bit determines whether a access permission violation was detected in this region. Read: No fault was detected. Write: No effect. Read: A fault was detected. Write: Clears the bit. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 778 Note: When using 64-bit transfers, the address is rounded up to the nearest 64-bit word end address, that is, 0x200 = 0x207. All other transfers are rounded up to the nearest 32-bit word end address. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 779 Note: When using 64-bit transfers, the address is rounded up to the nearest 64-bit word end address, that is, 0x200 = 0x207. All other transfers are rounded up to the nearest 32-bit word end address. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 780 Note: When using 64-bit transfers, the address is rounded up to the nearest 64-bit word end address, that is, 0x200 = 0x207. All other transfers are rounded up to the nearest 32-bit word end address. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 781 Note: When using 64-bit transfers, the address is rounded up to the nearest 64-bit word end address, that is, 0x200 = 0x207. All other transfers are rounded up to the nearest 32-bit word end address. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 782 Reads return 0. Writes have no effect. EDACMODE Disable correction of SBE detected by the SECDED block. Enable correction of SBE detected by the SECDED block. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 783 Write: No effect Note: The error address register will not be reset by PORRST nor by any other reset source. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 784 DMA is disabled by way of the DMA_EN bit. Up to 1 bit can be set in this register at any given time. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 785 DMA Request line 0, bit 1 corresponds to DMA Request line 1, and so on. DMA Request polarity is active high. DMA Request polarity is active low. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 786 Read: The associated TER Event of a channel is NOT pending. Write: No effect. Read: The associated TER Event of a channel is pending. Write: Clear this bit. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 787 Note: If both DMA ports encounter bus parity failure at the same time than lower channel number (assuming higher priority) will be stored and the other one will be ignored. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 788: Channel Configuration
Table 20-101. Initial Destination Address Register (IDADDR) Field Descriptions Field Description 31-0 IDADDR Initial destination address. These bits give the absolute 32-bit destination address (physical). Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 789 LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; X = value is unknown; -n = value after reset SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 790 Post-increment Reserved Indexed ADDMW Addressing mode write. Constant Post-increment Reserved Indexed Auto-initiation mode. Auto-initiation mode is disabled. Auto-initiation mode is enabled. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 791 Source address frame index. These bits define the offset to be added to the source address after element count reached 1. SPNU563A – March 2018 Direct Memory Access Controller (DMA) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 792 Current element transfer count. These bits return the current remaining element counts. CTCOUNT register is only updated after a channel is arbitrated out of the priority queue. Direct Memory Access Controller (DMA) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 793: External Memory Interface (Emif)
This chapter describes the external memory Interface (EMIF)..........................Topic Page ..................... 21.1 Introduction ................. 21.2 EMIF Module Architecture ....................21.3 EMIF Registers ..................21.4 Example Configuration SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 794: Introduction
Note that the EMIF module does not support Mobile SDRAM devices. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 795: Functional Block Diagram
SDRAM EMIF_nRAS interface EMIF_CLK EMIF_CKE EMIF_nCS[4:2] EDMA Asynchronous EMIF_nOE interface EMIF_nWAIT Master Peripherals EMIF_nWE EMIF_BA[1:0] Shared SDRAM EMIF_nDQM[1:0] and asynchronous interface EMIF_DATA[15:0] EMIF_ADDR[21:0] SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 796: Emif Module Architecture
When interfacing to an asynchronous device, these pins are connected to byte enables. See Section 21.2.6 for details. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 797: Emif Signal Multiplexing Control
Several EMIF signals are multiplexed with other functions on this microcontroller. Please refer to the I/O Multiplexing Module chapter of the technical reference manual for more information on how to enable the output of these EMIF signals. SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 798: Sdram Controller And Interface
EMIF_nCS[0] EMIF_nRAS EMIF_nCAS EMIF_nWE EMIF_BA[1:0] EMIF_A[12:11] EMIF_A[10] EMIF_A[9:0] Bank/X ACTV Bank READ Bank Column Column Bank Column Column Mode Mode Mode REFR SLFR External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 799 2M x 16 EMIF_nCS[0] x 4 bank EMIF_nCAS nCAS EMIF_nRAS nRAS EMIF_nWE EMIF_CLK EMIF_CKE EMIF_BA[1:0] BA[1:0] EMIF_A[11:0] A[11:0] EMIF_nDQM[0] LDQM EMIF_nDQM[1] UDQM EMIF_D[15:0] DQ[15:0] SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 800 SDRAM A[11:0] EMIF EMIF_A[11:0] 128M bits ×16 SDRAM A[11:0] EMIF EMIF_A[11:0] 256M bits SDRAM A[12:0] EMIF EMIF_A[12:0] 512M bits SDRAM A[12:0] EMIF EMIF_A[12:0] External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 801 • RR = f / (Required SDRAM Refresh Rate) EMIF_CLK More information about the operation of the SDRAM refresh controller can be found in Section 21.2.5.6. SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 802 6. Finally, the EMIF performs a refresh cycle, which consists of the following steps: a. Issuing a PRE command with EMIF_A[10] held high if any banks are open b. Issuing an REF command External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 803 200 μs (sometimes 100 μs). For example, an EMIF_CLK frequency of 100 MHz would require setting RR to 2501 (9C5h) or higher to meet a 200 μs constraint. SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 804 Multiple auto-refresh cycles are performed at the completion of the current access until the Refresh Release urgency level is reached. At that point, the EMIF can begin servicing any new read or write requests. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 805 EMIF_CLK. If the frequency of EMIF_CLK changes while the SDRAM is not in Self-Refresh Mode, Procedure B in Section 21.2.5.5 should be followed to reinitialize the device. SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 806 If the PD bit is cleared while in the power-down state, the EMIF will come out of the power-down state. The EMIF: • Drives EMIF_CKE high. • Enters its idle state. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 807 NOP commands between various commands during an access. Refer to the register description of SDTIMR in Section 21.3.6 for more details on the various timing parameters. SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 808 NOP commands during various cycles of an access. Refer to the register description of SDTIMR in Section 21.3.6 for more details on the various timing parameters. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 809 Row Address EMIF_BA[1:0] Column Address EMIF_nDQM[0] NOTE: The upper bit of the Row Address is used only when addressing 256-Mbit and 512-Mbit SDRAM memories. SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 810: Asynchronous Controller And Interface
EMIF's external pins used in interfacing with an asynchronous device. In EMIF_nCS[n], n = 2, 3, or 4. Figure 21-7. EMIF Asynchronous Interface EMIF EMIF_nCS[n] EMIF_nWE EMIF_nOE EMIF_WAIT EMIF_D[x:0] EMIF_nDQM[x:0] EMIF_A[x:0] EMIF_BA[1:0] External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 811 EMIF_BA[1] A[0] b) EMIF to 16-bit memory interface Figure 21-9. Common Asynchronous Interface EMIF 16−bit asynchronous device EMIF_nCS[n] EMIF_nWE EMIF_nDQM[1:0] BE[1:0] EMIF_D[15:0] DQ[15:0] SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 812 SDRAM accesses. Refer to the datasheet of the external asynchronous device to determine the appropriate setting for this field. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 813 (INTMSKSET). AT_MASK_CLR Asynchronous Timeout Mask Clear. Writing a 1 to this bit prevents an interrupt from being generated when an Asynchronous Timeout occurs. SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 814 If this is the case, the EMIF instead enters directly into the turnaround period for the pending read or write operation. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 815 Figure 21-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode Strobe Setup Hold EMIF_CLK EMIF_nCS[n] EMIF_nDQM Byte enable EMIF_A/EMIF_BA Address EMIF_D Data EMIF_nOE EMIF_nWE SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 816 If this is the case, the EMIF instead enters directly into the turnaround period for the pending read or write operation. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 817 Figure 21-11. Timing Waveform of an Asynchronous Write Cycle in Normal Mode Strobe Setup Hold EMIF_CLK EMIF_nCS[n] EMIF_nDQM Byte enable EMIF_A/EMIF_BA Address Address EMIF_D Data EMIF_nOE EMIF_nWE SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 818 If this is the case, the EMIF instead enters directly into the turnaround period for the pending read or write operation. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 819 Figure 21-12. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode Strobe Setup Hold EMIF_CLK EMIF_nCS[n] EMIF_nDQM Byte enables EMIF_A/EMIF_BA Address Data EMIF_D EMIF_nOE EMIF_nWE SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 820 If this is the case, the EMIF instead enters directly into the turn-around period for the pending read or write operation. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 821 R_SETUP and R_STROBE fields must be greater than 4 for the EMIF to recognize the EMIF_nWAIT pin has been asserted. The W_SETUP, W_STROBE, R_SETUP, and R_STROBE fields are in CEnCFG. SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 822: Data Bus Parking
For information about the self-refresh state, see Section 21.2.5.7. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 823: Reset And Initialization Considerations
Table 21-23 contains a brief summary of the interrupt status and control bit fields. See Section 21.3 for complete details on the register fields. SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 824: Dma Event Support
For details on EMIF signal multiplexing, see the I/O Multiplexing Module chapter of the technical reference manual. 21.2.12 Memory Map For information describing the device memory-map, see your device-specific datasheet. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 825: Priority And Arbitration
See Section 21.2.5.7 for details on the operation of the EMIF when in the self-refresh state. SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 826: System Considerations
If EMIF is used to interface to an external SDRAM, it is recommended to burst as much as possible to normal memory to improve the interface bandwidth. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 827: Power Management
EMIF in power down mode. 21.2.16 Emulation Considerations EMIF memory controller remains fully functional during emulation halts in order to allow emulation access to external memory. SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 828: Emif Registers
LEGEND: R = Read only; -n = value after reset Table 21-25. Module ID Register (MIDR) Field Descriptions Field Value Description 31-0 Module ID of EMIF. See the device-specific data manual. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 829: Asynchronous Wait Cycle Configuration Register (Awcc)
Maximum extended wait cycles. The EMIF will wait for a maximum of (MAX_EXT_WAIT + 1) × 16 clock cycles before it stops inserting asynchronous wait cycles and proceeds to the hold period of the access. SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 830: Sdram Configuration Register (Sdcr)
Reserved Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default value of 0. External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 831: Sdram Refresh Control Register (Sdrcr)
Writing a value < 0x0020 to this field will cause it to be loaded with (2 × T_RFC) + 1 value from the SDRAM timing register (SDTIMR). SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 832: Asynchronous N Configuration Registers (Ce2Cfg-Ce5Cfg)
Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. 8-bit data bus 16-bit data bus 2h-3h Reserved External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 833: Sdram Timing Register (Sdtimr)
Reserved Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default value of 0. SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 834: Sdram Self Refresh Exit Timing Register (Sdsretr)
This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, minus one. T_XS = Txsr / t EMIF_CLK External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 835: Emif Interrupt Raw Register (Intraw)
Indicates that an Asynchronous Timeout has occurred. Writing a 1 will clear this bit as well as the AT_MASKED bit in the EMIF interrupt masked register (INTMSK). SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 836: Emif Interrupt Masked Register (Intmsk)
Indicates that an Asynchronous Timeout Interrupt has been generated. Writing a 1 will clear this bit as well as the AT bit in the EMIF interrupt raw register (INTRAW). External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 837: Emif Interrupt Mask Set Register (Intmskset)
Indicates that the Asynchronous Timeout Interrupt is enabled. Writing a 1 sets this bit and the AT_MASK_CLR bit in the EMIF interrupt mask clear register (INTMSKCLR). SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 838: Emif Interrupt Mask Clear Register (Intmskclr)
Indicates that the Asynchronous Timeout Interrupt is enabled. Writing a 1 clears this bit and the AT_MASK_SET bit in the EMIF interrupt mask set register (INTMSKSET). External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 839: Page Mode Control Register (Pmcr)
Page Mode enable for NOR Flash connected on CS2. Page mode disabled for this chip select Page mode enabled for this chip select SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 840: Example Configuration
Table 21-37. SR Field Value For the EMIF to K4S641632H-TC(L)70 Interface Field Value Purpose 1 then 0 To place the EMIF into the self refresh state External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 841 A[12:1] DQ[15:0] EMIF_ADDR [18:13] nRESET Reset nRESET A[18:13] RY/BY nBYTE0 nBYTE1 FLASH A[0] 512k x 16 A[12:1] DQ[15:0] nRESET A[18:13] RY/BY nBYTE0 nBYTE1 SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 842 Figure 21-28. SDRAM Timing Register (SDTIMR) 0 0110 T_RFC T_RP Rsvd T_RCD Rsvd T_WR 0100 0110 0000 T_RAS T_RC Rsvd T_RRD Reserved External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 843 RR = 1562 cycles = 61Ah cycles EMIF_CLK Refresh Period Refresh Period = 64 ms; n = 4096 EMIF clock cycles cycles rate: f = 100 MHz EMIF_CLK SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 844 Figure 21-31. SDRAM Configuration Register (SDCR) 0 0000 Reserved Reserved Reserved 00 0000 Reserved Reserved Reserved Reserved Reserved Reserved BIT11_9LOCK Reserved IBANK Reserved PAGESIZE External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 845 EHEL Figure 21-33) Figure 21-32. LH28F800BJE-PTTL90 to EMIF Read Timing Waveforms Setup Hold Strobe EMIF_CLK EMIF_nCS[n] EMIF_A/ EMIF_BA EHQZ ELQV Data EMIF_D EMIF_nOE SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 846 For Writes, the W_STROBE field should be set to satisfy the Flash's nCE Pulse Width constraint, t ELEH W_STROBE >= t × f ELEH EMIF_CLK W_STROBE >= 50 ns × 100 MHz - 1 W_STROBE >= 4 External Memory Interface (EMIF) SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 847 Figure 21-34. Asynchronous m Configuration Register (m = 1, 2) (CEnCFG (n = 2, 3)) 0010 W_SETUP W_STROBE 0110 W_STROBE W_HOLD R_SETUP 001011 R_SETUP R_STROBE R_HOLD ASIZE SPNU563A – March 2018 External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 848: Analog To Digital Converter (Adc) Module
This chapter describes the analog to digital converter (ADC) interface module..........................Topic Page ......................22.1 Overview ....................22.2 Basic Operation ....................22.3 ADC Registers Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 849: Overview
External event pin (ADEVT) to trigger conversions – ADEVT is also programmable as general-purpose I/O • Eight hardware events to trigger conversions SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 850 Figure 22-1. Channel Assignments of Two ADC Cores AD1EXT_SEL[4:0] AD1EXT_ENA AD1EVT ADC1 AD1IN[7:0] 12 Bit AD1IN[15:8]/AD2IN[15:8] AD1IN[23:16]/AD2IN[7:0] AD1IN[31:24] CCAD SSAD REFHI REFLO AD2IN[24:16] ADC2 AD2EVT 12 Bit Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 851: Introduction
GP1_DMA_REQ Generation ADEVSRC.EV_SRC[2:0], ADG1SRC.G1_SRC[2:0], and ADG2SRC.G2_SRC[2:0] Event Trigger Results’ RAM Generation VBUS Interface for Access to ADC Registers and Results’ RAM SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 852 – - AD (27) REFHI REFLO 4096 x(InputVoltage - AD REFLO DigitalResult -------------------------------------------------------------------------------------- - 0.5 – - AD (28) REFHI REFLO Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 853: Basic Operation
VCLK by 1 up to 32. The ADCLK valid frequency range is specified in the device datasheet. / (PS + 1) ADCLK VCLK The maximum frequency for ADCLK is specified in the device datasheet. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 854 Group1 and Group2 as these can also be configured to be event-triggered. The polarity of the event trigger is also configurable, with a falling edge being the default. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 855 The CPU can read the conversion results in one of two ways: 1. By using the conversion results memory as a FIFO queue 2. By accessing the conversion results memory directly SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 856 F0h) returns the next result in the Event Group buffer but does not actually remove that result from the buffer or change the amount of data held in the buffer. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 857 FIFO. As a result, the application can selectively read the conversion results for any particular input channel of interest without having to read other channels’ conversion results. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 858 G1 RAM ADDR BNDB Channel 3 Channel 5 Channel 6 Channel 3 Channel 5 Group 2 Memory Channel 6 G2 RAM ADDR BNDEND Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 859 7. Read the conversion results by reading from the Group1 FIFO access location (ADG1BUFFER) or by reading directly from the Group1 results’ memory. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 860: Advanced Conversion Group Configuration Options
EV_MAX_COUNT Reserved 0x1A4 ADG1CURRCOUNT Reserved G1_CURRENT_COUNT Reserved 0x1A8 ADG1MAXCOUNT Reserved G1_MAX_COUNT Reserved 0x1AC ADG2CURRCOUNT Reserved G2_CURRENT_COUNT Reserved 0x1B0 ADG2MAXCOUNT Reserved G2_MAX_COUNT Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 861 22.2.2.2.1 Sequential Channel Selection Mode This is the default mode and allows the ADC module to be used in a backwards compatible mode to the ADC module on other Hercules™ ARM® Safety MCUs from Texas Instruments. As discussed in Section 22.2.1.4, an analog input channel can be selected for conversion in one or more conversion...
Page 862 ADC1 and 16 input channels for ADC2. If the application configures an unavailable channel number in the EV_INT_CHN_MUX_SEL field, the ADC will still perform the conversion and the result will be indeterminate. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 863 LUT index, 0 to 31 Reset when Current Count = Max Count Max Count Current Count Increment on End of Conversion ADGxSEL SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 864 The sequence proceeds as described whenever Group1 is next triggered, or if Group1 is configured to be in a continuous conversion mode. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 865 The priority of conversions between the three groups in descending order is: 1. Event Group 2. Group1 3. Group2 SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 866 – If the NoResetOnChnSel bit is 0, then the group’s FIFO will be reset. – If the NoResetOnChnSel bit is 1, then the group’s FIFO will not be reset. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 867 Therefore, the CHID bit for a group can be changed dynamically without affecting that group’s ongoing conversions. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 868: Adc Module Basic Interrupts
CPU or the DMA. Alternatively, the application program can set the group’s OVR_RAM_IGN bit and allow the ADC module to overwrite the group’s results’ memory contents with new conversion results. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 869: Adc Module Dma Requests
The group’s BLOCKS field is essentially the same as the group’s THRESHOLD field in the group’s interrupt control register described in Section 22.2.3.2. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 870: Adc Magnitude Threshold Interrupts
However, a read from the magnitude threshold interrupt offset register in emulation mode does not affect the interrupt flag register or the interrupt offset register. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 871: Adc Special Modes
The BRIDGE_EN and HILO bits (ADCALCR.9:8) control the voltage to the calibration reference device shown in Figure 22-15. The positions of the switches in calibration mode are listed in Table 22-2. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 872 7. Compute the error correction value using calibration data saved in memory. 8. Load the ADCALR register with the 2s complement of the computed error correction value. 9. Disable calibration mode. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 873 3. The actual value of the real middle point is obtained by computing the average of these two results. [D(cal1)+D(cal2)] /2; Figure 22-14 summarizes the mid-point calibration flow. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 874 However, the next channel in the sequence is converted correctly during the additional self-test cycle. The logic associated with both self-test and calibration is shown in Figure 22-15. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 875 ADREFLO is chosen as the reference voltage for the self-test mode conversion. It also assumes an external capacitor connected to the ADC input channel. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 876 , (see the specific device data sheet for actual value) has to be allowed before d(PU-ADV) starting a new conversion. This wait must be implemented in the application software. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 877 Figure 22-17. Timing for Sample Capacitor Discharge Mode Sample cap discharge time Sampling time Tdischarge T samp Conversion of last value sampled ADINx Vreflo Start SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 878: Adc Results' Ram Special Features
RAM. See Figure 22-18. The CPU can now manually insert parity errors. Note that the ADC RAM only supports 32-bit accesses. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 879: Adevt Pin General Purpose I/O Functionality
Figure 22-19. GPIO Functionality of ADxEVT Output enable ADxEVT Data out Data in Pull control disable Pull control logic Pull select SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 880 PULDIS = 0 for enabling pull control, 1 for disabling pull control PULSEL = 0 for pull-down functionality, 1 for pull-up functionality Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 881 Section 22.3.39 ADEVEMUBUFFER ADC Event Group Results Emulation FIFO Register Section 22.3.40 ADG1EMUBUFFER ADC Group1 Results Emulation FIFO Register Section 22.3.41 SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 882 ADC Group1 Max Count Register Section 22.3.75 1ACh ADG2CURRCOUNT ADC Group2 Current Count Register Section 22.3.76 1B0h ADG2MAXCOUNT ADC Group2 Max Count Register Section 22.3.77 Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 883 The ADC core and digital logic are configured to be in 12-bit resolution. 30-25 Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 884 No ADC conversions can occur. The input channel select registers: ADEVSEL, ADG1SEL, and ADG2SEL are held at their reset values. ADC conversions can now proceed as configured. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 885 R/W-0 R/W-0 Reserved CAL_EN R/W-0 LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 886 Section 22.2.6.1 for more details on the ADC calibration mode. Any operation mode read/write: Calibration mode is disabled. Calibration mode is enabled. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 887 EV_MODE FRZ_EV RAM_IGN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 888 The Event Group conversion result is read out as an 8-bit value in the “read from Event Group FIFO” mode. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 889 Group are converted before the ADC can switch over to servicing any other conversion group. Event Group conversions are frozen whenever there is a request for conversion from Group1 or Group2. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 890 FRZ_G1 RAM_IGN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 891 The hardware trigger for the Group1 is specified in the Group1 Trigger Source register (ADG1SRC). SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 892 ADC can switch over to servicing any other conversion group. Group1 conversions are frozen whenever there is a request for conversion from Event Group or Group2. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 893 FRZ_G2 RAM_IGN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 894 The hardware trigger for the Group2 is specified in the Group2 Trigger Source register (ADG2SRC). Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 895 ADC can switch over to servicing any other conversion group. Group2 conversions are frozen whenever there is a request for conversion from Event Group or Group1. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 896 The ADC module allows a trigger source to be selected for the Event Group from up to eight options. These options are device-specific and the device specification must be referred to identify the actual trigger sources. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 897 The ADC module allows a trigger source to be selected for the Group1 from up to eight options. These options are device-specific and the device specification must be referred to identify the actual trigger sources. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 898 The ADC module allows a trigger source to be selected for the Group2 from up to eight options. These options are device-specific and the device specification must be referred to identify the actual trigger sources. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 899 No interrupt is generated if the Event Group threshold counter reaches 0. An Event Group threshold interrupt is generated if the Event Group threshold counter reaches SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 900 No interrupt is generated if the Group1 threshold counter reaches 0. A Group1 threshold interrupt is generated if the Group1 threshold counter reaches 0. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 901 No interrupt is generated if the Group2 threshold counter reaches 0. A Group2 threshold interrupt is generated if the Group2 threshold counter reaches 0. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 902 Event Group interrupt threshold register. This bit can be cleared by writing a 1; writing a 0 has no effect. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 903 Group1 interrupt threshold register. This bit can be cleared by writing a 1; writing a 0 has no effect. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 904 Group2 interrupt threshold register. This bit can be cleared by writing a 1; writing a 0 has no effect. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 905 Group1 threshold counter is not decremented. Refer to Section 22.2.3.2 for more details on the threshold interrupts. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 906 Grou21 threshold counter is not decremented. Refer to Section 22.2.3.2 for more details on the threshold interrupts. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 907 Threshold Counter reaches 0 from a count value of 1. Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 908 ADC module generates a DMA transfer when the ADC has written to the Event Group memory. The EV_BLK_XFER bit must be cleared to 0 for this DMA request to be generated. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 909 Threshold Counter reaches 0 from a count value of 1. Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 910 ADC module generates a DMA transfer when the ADC has written to the Group1 memory. The G1_BLK_XFER bit must be cleared to 0 for this DMA request to be generated. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 911 Threshold Counter reaches 0 from a count value of 1. Reserved Reads return 0. Writes have no effect. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 912 ADC module generates a DMA transfer when the ADC has written to the Group2 memory. The G2_BLK_XFER bit must be cleared to 0 for this DMA request to be generated. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 913 A total of 2 × (BNDB - BNDA) buffers are available in the ADC results memory for storing Group1 conversion results. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 914 64 buffers each for ADC1 as well as ADC2. 4h-7h Reserved. These combinations must not be used. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 915 G1_ACQ value properly considering the frequency of the ADCLK signal. Refer to the device datasheet to determine the minimum sampling time for this device. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 916 G2_ACQ value properly considering the frequency of the ADCLK signal. Refer to the device datasheet to determine the minimum sampling time for this device. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 917 • By writing a 1 to this bit. • By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control register (ADOPMODECR). SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 918 • By writing a 1 to this bit. • By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control register (ADOPMODECR). Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 919 • By writing a 1 to this bit. • By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control register (ADOPMODECR). SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 920 The channels marked by the bit positions that are set to 1 will be converted in ascending order when the Event Group is triggered. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 921 The channels marked by the bit positions that are set to 1 will be converted in ascending order when the Group1 is triggered. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 922 The channels marked by the bit positions that are set to 1 will be converted in ascending order when the Group2 is triggered. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 923 ADC State Machine Current State. These bits reflect the current state of the state machine and are reserved for use by TI for debug purposes. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 924 A level higher than or equal to the midpoint reference voltage was measured at the last conversion for this channel. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 925 This allows the ARM LDMIA instruction to read out up to 8 conversion results from the Event Group results’ memory with just one instruction. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 926 ARM LDMIA instruction to read out up to 8 conversion results from the Group1 results’ memory with just one instruction. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 927 ARM LDMIA instruction to read out up to 8 conversion results from the Group2 results’ memory with just one instruction. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 928 The conversion result data is automatically shifted right by the appropriate number of bits when using a reduced-size data format with the upper bits reading as zeros. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 929 The conversion result data is automatically shifted right by the appropriate number of bits when using a reduced-size data format with the upper bits reading as zeros. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 930 The conversion result data is automatically shifted right by the appropriate number of bits when using a reduced-size data format with the upper bits reading as zeros. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 931 Any operating mode read/write: ADEVT is an input pin; the output buffer is disabled. ADEVT is an output pin; the output buffer is enabled. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 932 ADEVT Pin Input Value. This is a read-only bit that reflects the logic level on the ADEVT pin. Any operating mode read: Logic LOW present on the ADEVT pin. Logic HIGH present on the ADEVT pin. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 933 Output value on the ADEVT pin is unchanged. Output logic LOW on the ADEVT pin, if the pin is configured to be an output pin. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 934 Any operating mode read/write: Pull on ADEVT pin is enabled. Pull on ADEVT pin is disabled. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 935 After this discharge time has expired the selected ADC input channel is sampled and converted normally based on the Event Group settings. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 936 After this discharge time has expired the selected ADC input channel is sampled and converted normally based on the Group1 settings. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 937: Adc Group2 Sample Cap Discharge Control Register (Adg2Sampdisen)
After this discharge time has expired the selected ADC input channel is sampled and converted normally based on the Group2 settings. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 938: Adc Magnitude Compare Interrupt Control Registers (Admagintxcr)
COMP_CHIDx R/W-0 Reserved CHN_THR_ CMP_GE_LTx COMPx R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 939 The ADC module will check if the conversion result is greater than or equal to the reference value (fixed threshold or COMP_CHIDx conversion result). SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 940: Adc Magnitude Compare Interruptx Mask Register (Admagintxmask)
The ADC module will not mask the corresponding bit for the comparison. The ADC module will mask the corresponding bit for the comparison. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 941: Adc Magnitude Compare Interrupt Enable Set Register (Admagintenaset)
Any operation mode read/write for each bit: The enable status of the corresponding magnitude compare interrupt is left unchanged. The corresponding magnitude compare interrupt is disabled. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 942: Adc Magnitude Compare Interrupt Flag Register (Admagintflg)
Magnitude compare interrupt # 1 is pending. Magnitude compare interrupt # 2 is pending. Magnitude compare interrupt # 3 is pending. 4h-Fh Reserved. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 943: Adc Event Group Fifo Reset Control Register (Adevfiforesetcr)
If the application needs the Group1 memory to always be overwritten with the latest available conversion results, then the OVR_G1_RAM_IGN bit in the Group1 operating mode control register (ADG1MODECR) needs to be set to 1. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 944: Adc Group2 Fifo Reset Control Register (Adg2Fiforesetcr)
Event Group conversion result will be stored. This is specified in terms of the buffer number. The application can read this register to determine the number of valid Event Group conversion results available until that time. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 945: Adc Group1 Ram Write Address Register (Adg1Ramwraddr)
Group2 conversion result will be stored. This is specified in terms of the buffer number. The application can read this register to determine the number of valid Group2 conversion results available until that time. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 946: Adc Parity Control Register (Adparcr)
System module. Any operation mode read, privileged mode write: Parity check is disabled. All other values Parity check is enabled. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 947: Adc Parity Error Address Register (Adparaddr)
This register defines the number of VCLK cycles that the ADC state machine has to wait after releasing the ADC core from power down before starting a new conversion. Refer to Section 22.2.6.3 for more details. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 948: Adc Event Group Channel Selection Mode Control Register (Adevchnselmodectrl)
Group1, and the ADC module continues to use the channel selection mode that was previously programmed channel selection mode. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 949: Adc Group2 Channel Selection Mode Control Register (Adg2Chnselmodectrl)
Group2, and the ADC module continues to use the channel selection mode that was previously programmed channel selection mode. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 950: Adc Event Group Current Count Register (Adevcurrcount)
It is recommended to clear the Event group's CURRENT_COUNT register (ADEVCURRCOUNT) whenever the EV_MAX_COUNT is changed. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 951: Adc Group1 Current Count Register (Adg1Currcount)
It is recommended to clear the Group1's CURRENT_COUNT register (ADG1CURRCOUNT) whenever the G1_MAX_COUNT is changed. SPNU563A – March 2018 Analog To Digital Converter (ADC) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 952: Adc Group2 Current Count Register (Adg2Currcount)
It is recommended to clear the Group2's CURRENT_COUNT register (ADG2CURRCOUNT) whenever the G2_MAX_COUNT is changed. Analog To Digital Converter (ADC) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 953: High-End Timer (N2Het) Module
N2HET Functional Description ....................23.3 Angle Functions ................. 23.4 N2HET Control Registers 1017 ..................... 23.5 HWAG Registers 1044 ....................23.6 Instruction Set 1060 SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 954: Overview
Overview www.ti.com 23.1 Overview The N2HET is a fifth-generation Texas Instruments (TI) advanced intelligent timer module. It provides an enhanced feature set compared to previous generations. This timer module provides sophisticated timing functions for real-time applications such as engine management or motor control. The high resolution hardware channels allow greater accuracy for widely used timing functions such as period and pulse measurements, output compare, and PWMs.
Page 955: Block Diagram
HETFLG. 31:0 32 ALU Priority 2 HETOFF2.7:0 HETPRY.31:0 Rotate/ Shift by N HETDIN.31:0 HET[31:0] CONTROL HETDSET.31:0 HETDOUT.31:0 HETDIR.31:0 HETDCLR.31:0 HR clock HR block SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 956: Timer Module Structure And Execution
MOV32 instruction is actually executed which occurs after the ECMP instruction matches its current compare value. This is the same behavior as one would expect from a double buffered hardware compare register. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 957: Performance
There is a new instruction WCAPE, which is a combination of a time stamp and an edge counter • New Open Drain, Pull Disable, and Pull Select registers SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 958: Instructions Features
HR captures and compares are possible (up to N2HET clock accuracy) on the HR I/O pins. For more information about the HR I/O structure, see Section 23.2.5. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 959 HETOFF1.7:0 HETFLG. 31:0 Priority 2 T o VIM 32 Bit ALU HETOFF2.7:0 HETPRY.31:0 Rotate/ Shift By N Specialized timer micromachine To I/O Control SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 960 However other actions of the instruction including register and RAM updates will still be performed. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 961 MOV64 instruction in each low resolution loop, is required to control this particular program flow. NOTE: HR instructions must be placed in the main (full resolution) loop to ensure proper operation. SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 962 The current N2HET instruction address can be inspected by reading the HETADDR register; this should be pointing to the instruction that caused the breakpoint. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 963: N2Het Ram Organization
Table 23-1. N2HET RAM Base Addresses N2HET1 Base Address N2HET2 Base Address Memory 0xFF46_0000 0xFF44_0000 N2HET Instruction RAM (Program/Control/Data) 0xFF46_2000 0xFF44_2000 N2HET Parity RAM SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 964 NOTE: The external host interface supports any access size for reads, but only 32-bit writes to the N2HET RAM are supported. Reserved addresses should not be accessed, the result of doing so is indeterminate. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 965 Table 23-3. Pin Safe State Upon Parity Error Detection Safe State HETDIR HETPDR HETPSL Drive Low Drive High High Impedance SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 966: Time Base
N2HET program must fit into one loop resolution clock period (LRP).A 3-bit prescaler dividing the HR clock by a user-defined loop-resolution prescale divide rate (lr) stored in the 3-bit loop-resolution prescale factor code (HETPFR). See Table 23-5. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 967 LRPFC - Loop Resolution HRPFC - High Resolution HETPFR[10:8] Prescale Factor lr HETPFR[5:0] Prescale Factor hr 000000 000001 000010 000011 111101 111110 /128 111111 SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 968 0 to 31 1/16 1/32 1/64 0 to 63 1/16 1/32 1/64 1/128 0 to 127 X = Non-relevant bit (treated as '0') High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 969: Host Interface
SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 970: I/O Control
Data Set Register (HETDSET) or N2HET Data Clear Register (HETDCLR) for writing, depending on the type of action to perform. The N2HET pins used as general-purpose inputs are sampled on each VCLK2 period. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 971 1, hr_data = 0x0 } ; 25 bit compare value is 1 and the 7-bit HR compare value is 0 SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 972 HR mode (bit cleared to 0), but the other instructions can be used in standard resolution mode (bit set to 1). High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 973 HR prescale driver HR control logic Resolution clock Structure HR flags One Per HR up/down counter (7 bits) HR compare data HR register SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 974 The HET[1] HR structure is also connected to the HET[0] pin. The L00_PCNT data field is able to capture a high pulse and the L01_PCNT captures a low pulse on the same pin (N2HET [0] pin). High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 975 LH = (2291 - 653) · HRP = 1638 HRP • Duty cycle = DC = LH / PWM_period = 1638 HRP / (2944·HRP) = 55.6 % SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 976 Figure 23-15. AND-shared HR I/O HETAND0 N2HET HR 0 HET[0] HET[1] N2HET HR 1 HETAND0 High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 977 Output is output Buffer LBSEL[0] value determines whether or not loopback is enabled for these two blocks HR 1 Output Buffer Pin 1 SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 978 The loop back direction can be selected independent of the HETDIR register setting. • The pin that is not driven by the N2HET output pin actions can still be used as normal GIO pin. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 979 CNT and one ECMP instruction as shown below. The data field of the ECMP instruction is the 32-bit compare value, whereby the lower 7 bits represent the high resolution compare field. SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 980 MOV32. On execution of the MOV32, it moves its data field into the data field of the ECMP. The update of the duty cycle has to be made to the MOV32 data field instead of the ECMP data field. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 981 NOTE: The HR capture value written into RAM is shifted appropriately depending on the loop resolution prescale divide rate (lr). (See also Section 23.2.3.2). SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 982 Figure 23-22. PCNT Instruction Timing (With Capture Edge Before HR Counter Overflow) HR clock Loop res clock PCNT CF HR counter HR capt. PCNT DF Input pin Input pin sync’d High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 983 (2) is transferred to the valid bits (according the lr prescaler) of WCAP_DF[6:0]. Therefore, in the example 0x0240 is captured in WCAP_DF[31:0]. SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 984 The behavior of the input buffer, output buffer, and the pull control is summarized in Table 23-9. When an input buffer is disabled, it appears as a logic low to on-chip logic. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 985 HETDOUT N2HET pin HETDIN to other N2HET pin structures nDIS pin* N2HET pin enable *nDIS pin realized by GIOA[5] (N2HET1) and GIOB[2] (N2HET2) SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 986: Suppression Filters
• The accuracy of the output signal is +/- the counter clock frequency. Table 23-11 gives examples for a 100 MHz VCLK2 frequency. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 987: Interrupts And Exceptions
Source No. Offset Value no interrupt Instruction 0, 32, 64... Instruction 1, 33, 65... Instruction 31, 63, 95... Program Overflow APCNT underflow: APCNT overflow SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 988: Hardware Priority Scheme
The interrupt with the highest priority is the one with the lower offset value. This scheme is hard-wired in the offset encoder. See Figure 23-28. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 989 34 Exc Int En 2 Exc Int flag 2 Offset index encoder HET interrupt priority 2 for level 2 offset vector priority SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 990: N2Het Requests To Dma And Htu
ACNT accumulates the fractions generated by SCNT. Figure 23-30 illustrates the basic operation of APCNT, SCNT, and ACNT. A N2HET timer program can only have one angle generator. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 991 Figure 23-31. SCNT Count Operation Final Count = N0+nK Final Count = N1+mK Target=P(n-1) SCNT step counter N0+3K N1+2K N0+2K N1+K N0+K N2=N1+mK-P(n-1) N1=N0+nK-P(n-1) SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 992 Figure 23-32. ACNT Period Variation Compensations Deceleration Acceleration HET[2] ext. ref. signal P(n) APCNT P(n+1) period counter SCNT step counter ACNT angle generator Deceleration flag Acceleration flag High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 993 Figure 23-33. N2HET Timings Associated with the Gap Flag (ACNT Deceleration) Singularity HET[2] ext. ref. signal APCNT period counter Decel flag ACNT angle generator Gap flag Gap End Gap Start SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 994 APCNT overflow interrupt flag located in the exceptions interrupt control register. In this situation, SCNT and ACNT continue to be executed using the maximum APCNT period count. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 995: Hardware Angle Generator (Hwag)
Programmable toothed-wheel input filter • Programmable active edge on toothed-wheel • Start bit synchronized to the tooth edge • Pin selection capability for toothed-wheel input SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 996 Figure 23-36. Hardware Angle Generator Block Diagram HWAG To CPU ICLK Gap Veriﬁcation Toothed Wheel Angle Tick Generation Peripheral HWAG core HET Interface Angle increment HET Resolution To HET High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 997 Figure 23-37. Angle Tick Generation Principle Toothed wheel Angle Tick K Ticks P(n-1) P(n-1) P(n) SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 998 When encountering an earlier active edge, the ACNT accumulates the fractions (angle ticks) generated by the SCNT and the remainder of the TCKC. For an example of angle generation using the time-based algorithm, see Figure 23-39. High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 999 Final Count = N1+mK P(n-1) SCNT N1 +4K N0 +4K N1 +3K N0 +3K N1 +2K N0 +2K N1 +K N0 +K N1=N0+nK-P(n-1) N2=N1+mK-P(n-1) SPNU563A – March 2018 High-End Timer (N2HET) Module Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
Page 1000 When the ACNT contains a value equals to K times the teeth register, the PCNT, the TCNT and the ACNT are reset to begin a new revolution. 1000 High-End Timer (N2HET) Module SPNU563A – March 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...

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