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The boot protocol used in this mode is exactly the same as the C-Boot ROM SPI Master boot mode
explained in
Section
procedure explained in
ROM. The data format or data stream structure that M-Boot ROM expects the data to be coming in from
SSI slave is exactly same as defined in M-Boot ROM Parallel boot mode in
Note: M-Boot ROM Parallel Boot Mode, M-Boot ROM SSI0 Master Boot Mode and M-Boot ROM I2C0
Master boot mode are the boot modes similar to traditional C28x style booting with subtle differences. The
file formats supported by M-Boot ROM for these boot modes can be easily generated by the provided arm
hex tool chain, similar to how users do on C28x side with hex2000 utility.
6.5.15.9 M-Boot ROM OTP Boot Mode
If this boot mode is selected, Boot ROM branches to the OTP entry point as explained in
The function call sequence below gives details of the flow when OTP boot mode is selected on the device.
•
ResetIsr()
•
mbrom_init_device()
•
mbrom_master_system_init ()
•
mbrom_control_system_init()
•
mbrom_analog_system_init()
•
M-Boot ROM WIR Mode Check – Please refer to WIR Mode section in the _System Control and
Interrupts _chapter.
•
mbrom_get_bootmode()
•
mbrom_start_app(M_BOOT_ROM_OTP_ENTRY_POINT)
6.6
C-Boot ROM Description
The sequence followed by the control subsystem boot ROM is that it has to initialize the C28x CPU core,
initialize PIE to handle IPC commands from master and put C28x CPU in IDLE Low Power mode.
C-Boot ROM wakes up on an IPC interrupt from master subsystem, serves the IPC command and goes
back to IDLE or start the control subsystem application as commanded by the master.
6.6.1 C-Boot ROM Memory Map
The boot ROM is an 32K x 16 block of read-only memory located at addresses 0x3F 8000 - 0x3F FFFF.
The on-chip boot ROM is factory programmed with boot-load routines and both fixed-point and floating-
point math tables. These are for use with the C28x™ IQMath Library - A Virtual Floating Point Engine
(SPRC087) and the C28x FPU Fast RTS Library (SPRC664).
shows the memory map of the on-chip boot ROM. The memory block is 32Kx16 in size and is located at
0x3F 8000 - 0x3F FFFF in both program and data space.
SPRUHE8E – October 2012 – Revised November 2019
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6.6.15.5. The data transfer procedure explained in
Section 6.6.15.3
under C-Boot ROM sections is also followed here in M-Boot
Copyright © 2012–2019, Texas Instruments Incorporated
C-Boot ROM Description
Section 6.6.15.2
and data copy
Table
6-28.
Section
ROM Code and Peripheral Booting
6.5.7.9.
613
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