Clock Generation; I2C Module Conceptual Block Diagram - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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• A clock synchronizer to synchronize the I2C input clock (from the device clock generator) and the clock
on the SCL pin, and to synchronize data transfers with masters of different clock speeds
• A prescaler to divide down the input clock that is driven to the I2C module
• A noise filter on each of the two pins, SDA and SCL
• An arbitrator to handle arbitration between the I2C module (when it is a master) and another master
• Interrupt generation logic, so that an interrupt can be sent to the CPU
• FIFO interrupt generation logic, so that FIFO access can be synchronized to data reception and data
transmission in the I2C module
Figure 14-2 shows the four registers used for transmission and reception in non-FIFO mode. The CPU
writes data for transmission to I2CDXR and reads received data from I2CDRR. When the I2C module is
configured as a transmitter, data written to I2CDXR is copied to I2CXSR and shifted out on the SDA pin
one bit a time. When the I2C module is configured as a receiver, received data is shifted into I2CRSR and
then copied to I2CDRR.
SDA
SCL

14.1.4 Clock Generation

As shown in Figure
produces an I2C input clock with a programmed frequency. The I2C input clock is equivalent to the CPU
clock and is then divided twice more inside the I2C module to produce the module clock and the master
clock.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 14-2. I2C Module Conceptual Block Diagram
I2C module
I2CXSR I2CDXR
TX FIFO
RX FIFO
I2CRSR I2CDRR
Control/status
Clock
synchronizer
Prescaler
Noise filters
I2C INT
Arbitrator
14-3, the device clock generator receives a signal from an external clock source and
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registers
Introduction to the I2C Module
FIFO Interrupt
to CPU/PIE
Peripheral bus
CPU
Interrupt to
CPU/PIE
C28 Inter-Integrated Circuit Module
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