Usb Receive Interrupt Enable Register (Usbrxie), Offset 0X008; Usb Receive Interrupt Enable Register (Usbrxie); Usb Receive Interrupt Register (Usbrxie) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions

18.5.6 USB Receive Interrupt Enable Register (USBRXIE), offset 0x008

The USB receive interrupt enable 16-bit register (USBTXIE) provides interrupt enable bits for the interrupts
in the USBRXIS register. When a bit is set, the USB interrupt is asserted to the interrupt controller when
the corresponding interrupt bit in the USBRXIS register is set. When a bit is cleared, the interrupt in the
USBRXIS register is still set but the USB interrupt to the interrupt controller is not asserted. On reset, all
interrupts are enabled.
Mode(s): OTG A or Host
USBRXIE is shown in
15 14 13 12
EP15 EP14 EP13 EP12
R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-11. USB Receive Interrupt Register (USBRXIE) Field Descriptions
Bit Field
15 EP15
14 EP14
13 EP13
12 EP12
11 EP11
10 EP10
9 EP9
8 EP8
7 EP7
6 EP6
1346
M3 Universal Serial Bus (USB) Controller
OTG B or Device
Figure 18-7 and described in
Figure 18-8. USB Receive Interrupt Enable Register (USBRXIE)
11 10 9
EP11 EP10 EP9
R/W-1 R/W-1 R/W-1 R/W-1
Value Description
RX Endpoint 15 Interrupt Enable
0 The EP15 receive interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the EP15 bit in the USBRXIS register is set.
RX Endpoint 14 Interrupt Enable
0 The EP14 receive interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the EP14 bit in the USBRXIS register is set.
RX Endpoint 13 Interrupt Enable
0 The EP13 receive interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the EP13 bit in the USBRXIS register is set.
RX Endpoint 12 Interrupt Enable
0 The EP12 receive interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the EP12 bit in the USBRXIS register is set.
RX Endpoint 11 Interrupt Enable
0 The EP11 receive interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the EP11 bit in the USBRXIS register is set.
RX Endpoint 10 Interrupt Enable
0 The EP10 receive interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the EP10 bit in the USBRXIS register is set.
RX Endpoint 9 Interrupt Enable
0 The EP9 receive interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the EP9 bit in the USBRXIS register is set.
RX Endpoint 8 Interrupt Enable
0 The EP8 receive interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the EP8 bit in the USBRXIS register is set.
RX Endpoint 7 Interrupt Enable
0 The EP7 receive interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the EP7 bit in the USBRXIS register is set.
RX Endpoint 6 Interrupt Enable
0 The EP6 receive interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the EP6 bit in the USBRXIS register is set.
Copyright © 2012–2019, Texas Instruments Incorporated
Table 18-10.
8 7 6 5
EP8 EP7 EP6 EP5
R/W-1 R/W-1 R/W-1
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
4 3 2 1
EP4 EP3 EP2 EP1
R/W-1 R/W-1 R/W-1 R/W-1
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