Serial Communications Interface (Sci) Module Block Diagram - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Enhanced SCI Module Overview
• Auto-baud-detect hardware logic
• 16-level transmit/receive FIFO
Figure 13-2 shows the SCI module block diagram. The SCI port operation is configured and controlled by
the registers listed in
Figure 13-2. Serial Communications Interface (SCI) Module Block Diagram
Frame Format and Mode
Parity
Even/Odd Enable
SCICCR.6 SCICCR.5
TXWAKE
SCICTL1.3
1
WUT
SCIHBAUD. 15 − 8
Baud Rate
MSbyte
Register
LSPCLK
SCILBAUD. 7 − 0
Baud Rate
LSbyte
Register
SCIRXST.7 SCIRXST.4 − 2
RX Error
FE OE
RX Error
1018
C28 Serial Communications Interface (SCI)
Table 13-1 and Table 13-2.
SCICTL1.1
TXSHF
TXENA
Register
8
Transmitter−Data
Buffer Register
8
TX FIFO _0
TX FIFO _1
−−−−−
TX FIFO _15
SCITXBUF.7−0
TX FIFO registers
SCIFFENA
SCIFFTX.14
RXSHF
Register
RXENA
SCICTL1.0
8
Receive Data
Buffer register
SCIRXBUF.7−0
8
RX FIFO _15
−−−−−
RX FIFO_1
RX FIFO _0
SCIRXBUF.7−0
RX FIFO registers
RXFFOVF
SCIFFRX.15
PE
RX ERR INT ENA
SCICTL1.6
Copyright © 2012–2019, Texas Instruments Incorporated
SCITXD
TX EMPTY
SCICTL2.6
TXRDY
TX INT ENA
SCICTL2.7
SCICTL2.0
TX FIFO Interrupt
TX Interrupt
Logic
SCI TX Interrupt select logic
Auto baud detect logic
SCIRXD
RXWAKE
SCIRXST.1
SCICTL2.1
RXRDY
RX/BK INT ENA
SCIRXST.6
BRKDT
SCIRXST.5
RX Interrupt
RX FIFO Interrupt
Logic
SCI RX Interrupt select logic
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
SCITXD
TXINT
To CPU
SCIRXD
RXINT
To CPU
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