Usb Receive Control And Status Endpoint N Low Register (Usbrxcsrl[1]- Usbrxcsrl[15]); Usb Receive Control And Status Endpoint N Low Register (Usbcsrl[N]) In Otg A/Host Mode; Usb Control And Status Endpoint N Low Register(Usbcsrl[N]) In Otg A/Host Mode Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions
18.5.37 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]-
USBRXCSRL[15])
The USB receive control and status endpoint n low 8-bit register (USBCSRL[n]) provides control and
status bits for transfers through the currently selected receive endpoint.
For the specific offset for each register see
Mode(s): OTG A or Host
The USBCSRL[n] registers in OTG A/Host mode are shown in
Figure 18-46. USB Receive Control and Status Endpoint n Low Register (USBCSRL[n])
7 6
CLRDT STALLED
W1C-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 18-49. USB Control and Status Endpoint n Low Register(USBCSRL[n])
Bit Field Value
7 NAKTO
0
1
6 STALLED
0
1
5 REQPKT
0
1
4 FLUSH
0
1
3 DATAERR /
NAKTO
0
1
2 ERROR
0
1
1 FULL
0
1
1382
M3 Universal Serial Bus (USB) Controller
Table
OTG B or Device
in OTG A/Host Mode
5 4
REQPKT FLUSH
R/W-0 R/W-0
in OTG A/Host Mode Field Descriptions
Description
Clear Data Toggle.
No effect
Writing a 1 to this bit clears the DT bit in the USBRXCSRH[n] register.
Endpoint Stalled. Software must clear this bit.
No handshake has been received.
A STALL handshake has been received. The EPn bit in the USBRXIS register is also set.
Request Packet. This bit is cleared when the RXRDY bit is set.
No request
Requests an IN transaction.
Flush FIFO. If the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the
FIFO.
Note:This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be
corrupted.
No effect
Flushes the next packet to be read from the endpoint receive FIFO. The FIFO pointer is reset and the
RXRDY bit is cleared.
Data Error / NAK Timeout
Normal operation
Isochronous endpoints only: Indicates that RXRDY is set and the data packet has a CRC or bit-stuff
error. This bit is cleared when RXRDY is cleared.
Bulk endpoints only: Indicates that the receive endpoint is halted following the receipt of NAK responses
for longer than the time set by the NAKLMT field in the USBRXINTERVAL[n] register. Software must
clear this bit to allow the endpoint to continue.
Error. Software must clear this bit.
Note: This bit is only valid when the receive endpoint is operating in Bulk or Interrupt mode. In
Isochronous mode, it always returns zero.
No error
Three attempts have been made to receive a packet and no data packet has been received. The EPn
bit in the USBRXIS register is set in this situation.
FIFO Full
The receive FIFO is not full.
No more packets can be loaded into the receive FIFO.
Copyright © 2012–2019, Texas Instruments Incorporated
18-4.
Figure 18-46
3 2
DATAERR / ERROR
NAKTO
R/W-0 R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
and described in Table 18-49.
1 0
FULL RXRDY
R/W-0 R/W-0
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