Digital Compare Filter Offset Register (Dcfoffset); Digital Compare Filter Offset Counter Register (Dcfoffsetcnt); Digital Compare Counter Capture Register (Dccap) Field Descriptions; Digital Compare Filter Offset Register (Dcfoffset) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Registers
Table 7-72. Digital Compare Counter Capture Register (DCCAP) Field Descriptions
Bit Field
15-0 DCCAP
Figure 7-123. Digital Compare Filter Offset Register (DCFOFFSET)
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-73. Digital Compare Filter Offset Register (DCFOFFSET) Field Descriptions
Bit Field
15-0 OFFSET
Figure 7-124. Digital Compare Filter Offset Counter Register (DCFOFFSETCNT)
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-74. Digital Compare Filter Offset Counter Register (DCFOFFSETCNT) Field Descriptions
Bit Field
15-0 OFFSETCNT
808
C28 Enhanced Pulse Width Modulator (ePWM) Module
Value Description
0000-FFFFh Digital Compare Time-Base Counter Capture
To enable time-base counter capture, set the DCCAPCLT[CAPE] bit to 1.
If enabled, reflects the value of the time-base counter (TBCTR) on the low to high edge
transition of a filtered (DCEVTFLT) event. Further capture events are ignored until the
next period or zero as selected by the DCFCTL[PULSESEL] bit.
Shadowing of DCCAP is enabled and disabled by the DCCAPCTL[SHDWMODE] bit. By
default this register is shadowed.
• If DCCAPCTL[SHDWMODE] = 0, then the shadow is enabled. In this mode, the active
register is copied to the shadow register on the TBCTR = TBPRD or TBCTR = zero as
defined by the DCFCTL[PULSESEL] bit. CPU reads of this register will return the
shadow register value.
• If DCCAPCTL[SHDWMODE] = 1, then the shadow register is disabled. In this mode,
CPU reads will return the active register value.
The active and shadow registers share the same memory map address.
Value Description
0000- FFFFh Blanking Window Offset
These 16-bits specify the number of TBCLK cycles from the blanking window reference to
the point when the blanking window is applied. The blanking window reference is either
period or zero as defined by the DCFCTL[PULSESEL] bit.
This offset register is shadowed and the active register is loaded at the reference point
defined by DCFCTL[PULSESEL]. The offset counter is also initialized and begins to count
down when the active register is loaded. When the counter expires, the blanking window
is applied. If the blanking window is currently active, then the blanking window counter is
restarted.
OFFSETCNT
Value Description
0000- FFFFh Blanking Offset Counter
These 16-bits are read only and indicate the current value of the offset counter. The
counter counts down to zero and then stops until it is re-loaded on the next period or zero
event as defined by the DCFCTL[PULSESEL] bit.
The offset counter is not affected by the free/soft emulation bits. That is, it will always
continue to count down if the device is halted by a emulation stop.
Copyright © 2012–2019, Texas Instruments Incorporated
DCOFFSET
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SPRUHE8E – October 2012 – Revised November 2019
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