Counter-Compare C Register (Cmpc); Counter-Compare D Register (Cmpd); Counter-Compare B Register (Cmpb) Field Descriptions; Counter-Compare C Register (Cmpc) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Registers
Table 7-44. Counter-Compare B Register (CMPB) Field Descriptions
Bit Field Description
15-0 CMPB The value in the active CMPB register is continuously compared to the time-base counter (TBCTR). When the
values are equal, the counter-compare module generates a "time-base counter equal to counter compare B"
event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions.
These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration
of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB
registers include:
• Do nothing. event is ignored.
• Clear: Pull the EPWMxA and/or EPWMxB signal low
• Set: Pull the EPWMxA and/or EPWMxB signal high
• Toggle the EPWMxA and/or EPWMxB signal
Shadowing of this register is enabled and disabled by the CMPCTL[SHDWBMODE] bit. By default this
register is shadowed.
• If CMPCTL[SHDWBMODE] = 0, then the shadow is enabled and any write or read will automatically go to
• Before a write, the CMPCTL[SHDWBFULL] bit can be read to determine if the shadow register is currently
• If CMPCTL[SHDWBMODE] = 1, then the shadow register is disabled and any write or read will go directly
• In either mode, the active and shadow registers share the same memory map address.
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-45. Counter-Compare C Register (CMPC) Field Descriptions
Bit Field Description
15-0 CMPC The value in the active CMPC register is continuously compared to the time-base counter (TBCTR). When the
values are equal, the counter-compare module generates a "time-base counter equal to counter compare C"
event.
Shadowing of this register is enabled and disabled by the CMPCTL2[SHDWCMODE] bit. By default this
register is shadowed.
• If CMPCTL2[SHDWCMODE] = 0, then the shadow is enabled and any write or read will automatically go to
• If CMPCTL2[SHDWCMODE] = 1, then the shadow register is disabled and any write or read will go directly
• In either mode, the active and shadow registers share the same memory map address.
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
784
C28 Enhanced Pulse Width Modulator (ePWM) Module
the shadow register. In this case, the CMPCTL[LOADBMODE] bit field determines which event will load the
active register from the shadow register:
full.
to the active register, that is the register actively controlling the hardware.
Figure 7-95. Counter-Compare C Register (CMPC)
the shadow register. In this case, the CMPCTL2[LOADCMODE] bit field determines which event will load
the active register from the shadow register:
to the active register; that is, the register actively controlling the hardware.
Figure 7-96. Counter-Compare D Register (CMPD)
Copyright © 2012–2019, Texas Instruments Incorporated
CMPC
R/W-0
CMPD
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
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