Spi Operation Control Register (Spictl) - Address 7041H; Character Length Control Bit Values; Spi Operation Control Register (Spictl) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

SPI Registers and Waveforms
SPI CHAR3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
12.3.1.2 SPI Operation Control Register (SPICTL)
SPICTL controls data transmission, the SPI's ability to generate interrupts, the SPICLK phase, and the
operational mode (slave or master).
Figure 12-14. SPI Operation Control Register (SPICTL) — Address 7041h
7 6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-10. SPI Operation Control Register (SPICTL) Field Descriptions
Bit Field
7-5 Reserved
4 Overrun INT ENA
3 CLOCK PHASE
2 MASTER /
SLAVE
1002
C28 Serial Peripheral Interface (SPI)
Table 12-9. Character Length Control Bit Values
SPI CHAR2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
5 4
OVERRUN INT
ENA
R/W-0
Value Description
Reads return zero; writes have no effect.
Overrun Interrupt Enable. Setting this bit causes an interrupt to be generated when the RECEIVER
OVERRUN Flag bit (SPISTS.7) is set by hardware. Interrupts generated by the RECEIVER
OVERRUN Flag bit and the SPI INT FLAG bit (SPISTS.6) share the same interrupt vector.
0 Disable RECEIVER OVERRUN Flag bit (SPISTS.7) interrupts
1 Enable RECEIVER OVERRUN Flag bit (SPISTS.7) interrupts
SPI Clock Phase Select. This bit controls the phase of the SPICLK signal.
CLOCK PHASE and CLOCK POLARITY (SPICCR.6) make four different clocking schemes
possible (see Figure 12-4). When operating with CLOCK PHASE high, the SPI (master or slave)
makes the first bit of data available after SPIDAT is written and before the first edge of the SPICLK
signal, regardless of which SPI mode is being used.
0 Normal SPI clocking scheme, depending on the CLOCK POLARITY bit (SPICCR.6)
1 SPICLK signal delayed by one half-cycle; polarity determined by the CLOCK POLARITY bit
SPI Network Mode Control. This bit determines whether the SPI is a network master or slave.
During reset initialization, the SPI is automatically configured as a network slave.
0 SPI configured as a slave.
1 SPI configured as a master.
Copyright © 2012–2019, Texas Instruments Incorporated
SPI CHAR1 SPI CHAR0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
3
CLOCK MASTER/
PHASE SLAVE
R/W-0 R/W-0
SPRUHE8E – October 2012 – Revised November 2019
Character Length
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2 1
TALK SPI INT ENA
R/W-0
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0
R/W-0