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21.7.14 UART DMA Control (UARTDMACTL), offset 0x048
The UARTDMACTL register is the DMA control register.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21-16. UART DMA Control (UARTDMACTL) Register Field Descriptions
Bit
Field
31-3
Reserved
2
DMAERR
1
TXDMAE
0
RXDMAE
21.7.15 UART LIN Control (UARTLCTL), offset 0x090
The UARTLCTL register is the configures the operation of the UART when in LIN mode.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21-17. UART LIN Control (UARTLCTL) Register Field Descriptions
Bit
Field
31-6
Reserved
5-4
BLEN
3-1
Reserved
0
MASTER
SPRUHE8E – October 2012 – Revised November 2019
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Figure 21-21. UART DMA Control (UARTDMACTL) Register
Reserved
R-0
Value
Description
Reserved
DMA on Error
0
µDMA receive requests are unaffected when a receive error occurs.
1
µDMA receive requests are automatically disabled when a receive error occurs.
Transmit DMA Enable
0
µDMA for the transmit FIFO is disabled.
1
µDMA for the transmit FIFO is enabled.
Receive DMA Enable
0
µDMA for the receive FIFO is disabled.
1
µDMA for the receive FIFO is enabled.
Figure 21-22. UART LIN Control (UARTLCTL) Register
Reserved
R-0
Value
Description
Reserved
Sync Break Length
0x3
Sync break length is 16T bits
0x2
Sync break length is 15T bits
0x1
Sync break length is 14T bits
0x0
Sync break length is 13T bits (default)
Reserved
LIN Master Enable
0
The UART operates as a LIN slave.
1
The UART operates as a LIN master.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3
2
DMAERR
R/W-0
Reserved
R-0
6
5
BLEN
R/W-0
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Register Descriptions
1
0
TXDMAE
RXDMAE
R/W-0
R/W-0
4
3
1
0
Reserved
MASTER
R-0
R/W-0
16
16
1515
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