Gpio Port G Set, Clear And Toggle (Gpgset, Gpgclear, Gpgtoggle) Registers; Gpio Port G Set (Gpgset) Register Field Descriptions; Gpio Port G Clear (Gpgclear) Register Field Descriptions; Gpio Port G Toggle (Gpgtoggle) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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C28 General-Purpose Input/Output (GPIO)

4.2.7.50 GPIO Port G Set, Clear and Toggle (GPGSET, GPGCLEAR, GPGTOGGLE) Registers

The GPIO Port G Set, Clear and Toggle (GPGSET, GPGCLEAR, GPGTOGGLE) registers are shown and

described in the figure and table below.

Figure 4-91. GPIO Port G Set, Clear and Toggle (GPGSET, GPGCLEAR, GPGTOGGLE) Registers

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-110. GPIO Port G Set (GPGSET) Register Field Descriptions

GPIO199 -GPIO192

Table 4-111. GPIO Port G Clear (GPGCLEAR) Register Field Descriptions

GPIO199 -GPIO192

Table 4-112. GPIO Port G Toggle (GPGTOGGLE) Register Field Descriptions

GPIO199 -GPIO192

General-Purpose Input/Output (GPIO)

Any writes to these bit(s) must always have a value of 0.

Each GPIO port G pin (GPIO199 -GPIO192) corresponds to one bit in this register.

Writes of 0 are ignored. This register always reads back a 0.

Writing a 1 forces the respective output data latch to high. If the pin is configured as a GPIO

output then it will be driven high. If the pin is not configured as a GPIO output then the latch is

set but the pin is not driven.

Any writes to these bit(s) must always have a value of 0.

Each GPIO port G pin (GPIO199 -GPIO192) corresponds to one bit in this register.

Writes of 0 are ignored. This register always reads back a 0.

Writing a 1 forces the respective output data latch to low. If the pin is configured as a GPIO

output then it will be driven low. If the pin is not configured as a GPIO output then the latch is

cleared but the pin is not driven.

Any writes to these bit(s) must always have a value of 0.

Each GPIO port G pin (GPIO199 -GPIO192) corresponds to one bit in this register.

Writes of 0 are ignored. This register always reads back a 0.

Writing a 1 forces the respective output data latch to toggle from its current state. If the pin is

configured as a GPIO output then it will be driven in the opposite direction of its current state. If

the pin is not configured as a GPIO output then the latch is cleared but the pin is not driven.

SPRUHE8E – October 2012 – Revised November 2019

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