Clocking Control Registers; System Pll Multiplier (Syspllmult) Register; System Clock Divider (Sysdivsel) Register; System Pll Multiplier (Syspllmult) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

System Control Registers
Table 1-106. C28_USER_SWREG2 Register Field Descriptions (continued)
Bit Field
7-0 SWREG2

1.13.7 Clocking Control Registers

1.13.7.1 System PLL Multiplier (SYSPLLMULT) Register

31
15
Reserved
R-0:0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-107. System PLL Multiplier (SYSPLLMULT) Register Field Descriptions
Bit Field
31-10 Reserved
9-8 SPLLFMULT
7 Reserved
6-0 SPLLIMULT

1.13.7.2 System Clock Divider (SYSDIVSEL) Register

31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
226
System Control and Interrupts
Value Description
General purpose register for C28 software use.
0
1
Figure 1-96. System PLL Multiplier (SYSPLLMULT) Register
10 9
SPLLFMULT
R/W-0:0
Value Description
Reserved
System PLL Fractional Mutliplier
00 Fractional multiplier = 0
01 Fractional multiplier = 0.25
10 Fractional multiplier = 0.5
11 Fractional multiplier = 0.75
Reserved
System PLL Integer Multiplier
0000000 Integer multiplier = 1
0000001 Integer multiplier = 1
0000010 Integer multiplier = 2
0000011 Integer multiplier = 3
... ...
1111111 Integer multipler = 127
Figure 1-97. System Clock Divider (SYSDIVSEL) Register
Reserved
R-0:0
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0:0
8 7 6
Rsvd
R-0
Reserved
R-0x1
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
SPLLIMULT
R/W-0:0
2 1
SYSDIVSEL
R/W-11
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16
0
16
0