Master Transmit With Repeated Start - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Functional Description
Idle
Write Slave
Address and
Transmit Bit to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
NO
BUSBSY bit=0?
YES
Write 011
to I2CMCS
1530
M3 Inter-Integrated Circuit (I2C) Interface
Figure 22-9. Master TRANSMIT with Repeated START
Sequence
may be
omitted in a
Single Master
system
Write 001
to I2CMCS
Error Service
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Read I2CMCS
NO
BUSY bit=0?
YES
NO
ERROR bit=0?
YES
Write data to
I2CMDR
NO
Index=n?
YES
Write 101
to I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
NO
ERROR bit=0?
YES
Idle
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
NO
ARBLST bit=1?
YES
Write 100
to I2CMCS
Error Service
Idle
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