Ram Control Module; Functional Description; Ram Control - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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5.1

RAM Control Module

For these devices, the RAMs have different characteristics. Some are dedicated to a particular master
CPU; some are shared between a CPU and its DMA; and, some are shared between both CPUs and both
DMAs.
All these RAMs are highly configurable to achieve control for write access and fetch access from different
masters. There are also RAMs - called IPC MSGRAMs - that are used for interprocessor communication.
All dedicated RAMs are enabled with the ECC feature (both data and addr) and shared RAMs are enabled
with the PARITY (both data and addr) feature. Some of the dedicated memories are secure memory as
well. Refer to the Security section of the System Control and Interrupts chapter for more details. Each
RAM has its own controller which takes care of the access protection/security related checks and
ECC/Parity features for that RAM.
NOTE: All RAMs on Concerto devices are SRAMs.

5.1.1 Functional Description

This section further defines and discusses the dedicated RAMs, shared RAMs, and MSG RAMs on this
device.
5.1.1.1 Dedicated RAM
The M3 subsystem has two dedicated RAM blocks: C0 and C1. Only the Cortex-M3 CPU has access to
these memories. No other masters (including µDMA) have any access to these memories.
The C28x subsystem has four dedicated RAM blocks: M0, M1, L0, and L1. M0/M1 memories are small
blocks of memory which are tightly coupled with the CPU. Only the C28x CPU has access to these
memories. No other masters (including DMA) have any access to these memories.
All dedicated RAMs have the ECC feature. All dedicated memories (except for M0/M1) are secure
memory and also have the access protection (cpu write protection/cpu fetch protection) feature. Each type
of access protection for each RAM block can be enabled/disabled by configuring the specific bit in the
RAM block configuration register, allocated to each subsystem (CxDRCR for the M3 subsystem and
LxDRCR for the C28x subsystem).
5.1.1.2 Shared RAM
RAM blocks which can be accessed by more than one master (CPU or DMA) are called shared RAMs. On
these devices, all such memories are non-secure memory and have the parity feature.
There are different types of shared RAMs. The first type of Shared RAMs are dedicated to each
subsystem and have access from the respective CPU and DMA only (see
on the M3 subsystem are mapped to the M3 CPU and M3 µDMA. Similarly for the C28x subsystem, these
RAM blocks are mapped to the C28 CPU and C28 DMA.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 5-1 shows the configuration of these RAMs.
Figure 5-1. RAM Control
RAM Configuration

RAM Control

M0
Arbitration/
Security
Checks/
Access
Protection
Mn
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S
ECC/
R
Parity
A
M
Figure 5-2). Such RAM blocks
RAM Control Module
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Internal Memory