Pie, Intx Group Flag Register (Pieifrx) (X = 1 To 12); Pie, Intx Group Flag Register (Pieifrx) (X = 1 To 12) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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1.13.5.13.4 PIE Interrupt Flag Registers

There are twelve PIEIFR registers, one for each CPU interrupt used by the PIE module (INT1-INT12).

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1-87. PIE, INTx Group Flag Register (PIEIFRx) (x = 1 to 12) Field Descriptions

These register bits indicate whether an interrupt is currently active. They behave very much like the CPU

interrupt flag register. When an interrupt is active, the respective register bit is set. The bit is cleared when the

interrupt is serviced or by writing a 0 to the register bit. This register can also be read to determine which

interrupts are active or pending. x = 1 to 12. INTx means CPU INT1 to INT12

The PIEIFR register bit is cleared during the interrupt vector fetch portion of the interrupt processing.

Hardware has priority over CPU accesses to the PIEIFR registers.

NOTE: Never clear a PIEIFR bit. An interrupt may be lost during the read-modify-write operation.

1.13.5.13.5 CPU Interrupt Flag Register (IFR)

The CPU interrupt flag register (IFR), is a 16-bit, CPU register and is used to identify and clear pending

interrupts. The IFR contains flag bits for all the maskable interrupts at the CPU level (INT1-INT14,

DLOGINT and RTOSINT). When the PIE is enabled, the PIE module multiplexes interrupt sources for

When a maskable interrupt is requested, the flag bit in the corresponding peripheral control register is set

to 1. If the corresponding mask bit is also 1, the interrupt request is sent to the CPU, setting the

corresponding flag in the IFR. This indicates that the interrupt is pending or waiting for acknowledgment.

To identify pending interrupts, use the PUSH IFR instruction and then test the value on the stack. Use the

OR IFR instruction to set IFR bits and use the AND IFR instruction to manually clear pending interrupts.

All pending interrupts are cleared with the AND IFR #0 instruction or by a hardware reset.

The following events also clear an IFR flag:

The CPU acknowledges the interrupt.

The 28x device is reset.

SPRUHE8E – October 2012 – Revised November 2019

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Figure 1-76. PIE, INTx Group Flag Register (PIEIFRx) (x = 1 to 12)

Section 1.5.4.3.1

for a method to clear flagged interrupts.

System Control Registers

System Control and Interrupts

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