M3 Sx Shram Configuration Register 2 (Msxsrcr2); M3 Sx Shram Configuration Register 2 (Msxsrcr2) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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RAM Control Module Registers

M3 Sx SHRAM Configuration Register 2 (MSxSRCR2)

Figure 5-11. M3 Sx SHRAM Configuration Register 2 (MSxSRCR2)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-20. M3 Sx SHRAM Configuration Register 2 (MSxSRCR2) Field Descriptions

Internal Memory

CPU Write Protection S7

M3 CPU write allowed to S7 RAM block.

M3 CPU write not allowed to S7 RAM block.

µDMA Write Protection S7

M3 µDMA write allowed to S7 RAM block.

M3 µDMA write not allowed to S7 RAM block.

CPU Fetch Protection S7

M3 CPU Fetch allowed from S7 RAM block.

M3 CPU Fetch not allowed from S7 RAM block.

CPU Write Protection S6

M3 CPU write allowed to S6 RAM block.

M3 CPU write not allowed to S6 RAM block.

µDMA Write Protection S6

M3 µDMA write allowed to S6 RAM block.

M3 µDMA write not allowed to S6 RAM block.

CPU Fetch Protection S6

M3 CPU Fetch allowed from S6 RAM block.

M3 CPU Fetch not allowed from S6 RAM block.

CPU Write Protection S5

M3 CPU write allowed to S5 RAM block.

M3 CPU write not allowed to S5 RAM block.

µDMA Write Protection S5

M3 µDMA write allowed to S5 RAM block.

M3 µDMA write not allowed to S5 RAM block.

SPRUHE8E – October 2012 – Revised November 2019

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