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Host Bus Mode
Figure 17-7
shows how to connect the EPI signals to a16-bit SRAM and a 16-bit Flash memory with
muxed address and memory using byte selects and dual chip selects with ALE. This schematic is just an
example of how to connect the signals; timing and loading have not been analyzed. In addition, not all
bypass capacitors are shown.
CLOCK
(EPI0S31)
IRDY
(EPI0S32)
State
IRDYDLY = 01
IRDYDLY = 10
IRDYDLY = 11
1246
External Peripheral Interface (EPI)
Figure 17-5. iRDY Access Stalls
Data B
Data C
Data A
Data A
Data B
Data A
Data B
Data A
Data B
Data C
Figure 17-6. iRDY Signal Connection
Cellular RAM
IRDY
WAIT
Other
Processor
Device
Copyright © 2012–2019, Texas Instruments Incorporated
Data D
Data E
Data C
Data D
Data C
Data D
Data D
WAIT
WAIT
Other
Device
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Data F
Data E
Data E
Data E
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